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74HC32PW

Description
Logic Gates QUAD 2-INPUT OR GATE
Categorylogic    logic   
File Size132KB,17 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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74HC32PW Overview

Logic Gates QUAD 2-INPUT OR GATE

74HC32PW Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerNXP
Objectid1440954794
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP14,.25
Contacts14
Reach Compliance Codecompliant
compound_id10103153
seriesHC/UH
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeOR GATE
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTUBE
Peak Reflow Temperature (Celsius)260
power supply2/6 V
Prop。Delay @ Nom-Sup27 ns
propagation delay (tpd)135 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNICKEL PALLADIUM GOLD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
74HC32; 74HCT32
Quad 2-input OR gate
Rev. 5 — 4 September 2012
Product data sheet
1. General description
The 74HC32; 74HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
V
CC
.
2. Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
Complies with JEDEC standard JESD7A
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
Input levels:
For 74HC32: CMOS level
For 74HCT32: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C

74HC32PW Related Products

74HC32PW 74HC32DB
Description Logic Gates QUAD 2-INPUT OR GATE Logic Gates QUAD 2-INPUT OR GATE
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker NXP NXP
Parts packaging code TSSOP SSOP
package instruction TSSOP, TSSOP14,.25 SSOP, SSOP14,.3
Contacts 14 14
Reach Compliance Code compliant unknown
series HC/UH HC/UH
JESD-30 code R-PDSO-G14 R-PDSO-G14
JESD-609 code e4 e4
length 5 mm 6.2 mm
Load capacitance (CL) 50 pF 50 pF
Logic integrated circuit type OR GATE OR GATE
MaximumI(ol) 0.004 A 0.004 A
Humidity sensitivity level 1 1
Number of functions 4 4
Number of entries 2 2
Number of terminals 14 14
Maximum operating temperature 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP SSOP
Encapsulate equivalent code TSSOP14,.25 SSOP14,.3
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
method of packing TUBE TUBE
Peak Reflow Temperature (Celsius) 260 260
power supply 2/6 V 2/6 V
Prop。Delay @ Nom-Sup 27 ns 27 ns
propagation delay (tpd) 135 ns 135 ns
Certification status Not Qualified Not Qualified
Schmitt trigger NO NO
Maximum seat height 1.1 mm 2 mm
Maximum supply voltage (Vsup) 6 V 6 V
Minimum supply voltage (Vsup) 2 V 2 V
Nominal supply voltage (Vsup) 5 V 5 V
surface mount YES YES
technology CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE
Terminal surface NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 30
width 4.4 mm 5.3 mm
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