DSP56852 General Description
• 120 MIPS at 120MHz
• 6K x 16-bit Program SRAM
• 4K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• 21 External Memory Address lines, 16 data lines and
four chip selects
• One (1) Serial Port Interface (SPI) or one (1) Improved
Synchronous Serial Interface (ISSI)
• One (1) Serial Communication Interface (SCI)
• Interrupt Controller
• General Purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog Timer
• 81-pin MAPBGA package
• Up to 11 GPIO
6
V
DDIO
6
V
DD
3
V
SSIO
6
V
SS
V
DDA
3
V
SSA
JTAG/
Enhanced
OnCE
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
16-Bit
56800E Core
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
Memory
Program Memory
6144 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
4096 x 16 SRAM
R/W Control
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
System
Bus
Control
System
Address
Decoder
System
Device
IPBus Bridge (IPBB)
RW
Control
IPAB
IPWDB
IPRDB
Peripheral
Address
Decoder
Decoding
Peripherals
A0-16
A17-18 muxed (timer pins)
A19 muxed (CS3)
D0-D12[12:0]
D13-15 muxed (Mode A,B,C)
WR Enable
RD Enable
CS[2:0] muxed (GPIOA)
External Address
Bus Switch
External Data
Bus Switch
External Bus
Interface Unit
Peripheral
Device
Selects
Clock
resets
P
O
R
PLL
SCI or
GPIOE
Bus Control
1 Quad
Timer
or A17,
A18
SSI or
SPI or
GPIOC
COP/
Watch-
dog
Interrupt
Controller
System
Integration
Module
Clock
Generator
O
S
C
XTAL
EXTAL
2
2
6
IRQA
IRQB
3
CLKO
RESET
muxed
(A20)
MODE
muxed (D13-15)
56852 Block Diagram
56852 Technical Data, Rev. 8
Freescale Semiconductor
3
Part 1 Overview
1.1 56852 Features
1.1.1
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Core
Efficient 16-bit engine with dual Harvard architecture
120 Million Instructions Per Second (MIPS) at 120MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four (4) 36-bit accumulators including extension bits
16-bit bidirectional shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three (3) internal address buses and one (1) external address bus
Four (4) internal data buses and one (1) external data bus
Instruction set supports both DSP and controller functions
Four (4) hardware interrupt levels
Five (5) software interrupt levels
Controller-style addressing modes and instructions for compact code
Efficient C Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced OnCE debug programming interface
1.1.2
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Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
On-chip memory includes:
— 6K
×
16-bit Program SRAM
— 4K
×
16-bit Data SRAM
— 1K
×
16-bit Boot ROM
21 External Memory Address lines, 16 data lines and four (4) programmable chip select signals
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1.1.3
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Peripheral Circuits for DSP56852
General Purpose 16-bit Quad Timer with two external pins*
One (1) Serial Communication Interface (SCI)*
One (1) Serial Port Interface (SPI) or one (1) Improved Synchronous Serial Interface (ISSI) module*
Interrupt Controller
Computer Operating Properly (COP)/Watchdog Timer
JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging
81-pin MAPBGA package
Up to 11 GPIO
* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed
56852 Technical Data, Rev. 8
4
Freescale Semiconductor
56852 Description
1.1.4
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Energy Information
Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs
Wait and Stop modes available
1.2 56852 Description
The 56852 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the
processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56852 is well-suited for many applications. The
56852 includes many peripherals especially useful for low-end Internet appliance applications and
low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale systems
such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices; remote
metering; and sonic alarms.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact DSP and
control code. The instruction set is also highly efficient for C-Compilers, enabling rapid development of
optimized control applications.
The 56852 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56852 also provides two external
dedicated interrupt lines, and up to 11 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56852 includes 6K words of Program RAM, 4K words of Data RAM and 1K of Boot RAM. It also
supports program execution from external memory.
This controller also provides a full set of standard programmable peripherals that include one improved
Synchronous Serial Interface (SSI) or one Serial Peripheral Interface (SPI), one Serial Communications
Interface (SCI), and one Quad Timer. The SSI, SPI, SCI I/O and three chip selects can be used as General
Purpose Input/Outputs when its primary function is not required. The SSI and SPI share I/O, so, at most,
one of these two peripherals can be in use at any time.
1.3 State of the Art Development Environment
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Processor Expert
TM
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
56852 Technical Data, Rev. 8
Freescale Semiconductor
5
FPGA/CPLD
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