DS26303
3.3V, E1/T1/J1, Short-Haul,
Octal Line Interface Unit
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26303 is an 8-channel short-haul line
interface unit (LIU) that supports E1/T1/J1 from a
single 3.3V power supply. A wide variety of
applications are supported through internal
termination or external termination. A single bill of
material can support E1/T1/J1 with minimum external
components. Redundancy is supported through
nonintrusive monitoring, optimal high-impedance
modes, and configurable 1:1 or 1+1 backup
enhancements. An on-chip synthesizer generates the
E1/T1/J1 clock rates by a single master clock input of
various frequencies. Two clock output references are
also offered.
FEATURES
8 Complete E1, T1, or J1 Short-Haul Line
Interface Units
Independent E1, T1, or J1 Selections
Internal Software-Selectable Transmit and
Receive-Side Termination
Crystal-Less Jitter Attenuator
Selectable Single-Rail and Dual-Rail Mode
and AMI or HDB3/B8ZS Line Encoding and
Decoding
Detection and Generation of AIS
Digital/Analog Loss-of-Signal Detection as
per T1.231, G.775, and ETS 300 233
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock will be Internally
Adapted for T1 or E1 Use
Built-In BERT Tester for Diagnostics
8-Bit Parallel Interface Support for Intel or
Motorola Mode or a 4-Wire Serial Interface
Hardware Mode Interface Support
Transmit Short-Circuit Protection
G.772 Nonintrusive Monitoring
Specification Compliance to the Latest T1
and E1 Standards—ANSI T1.102, AT&T Pub
62411, T1.231, T1.403, ITU-T G.703, G.742,
G.775, G.823, ETS 300 166, and ETS 300 233
Single 3.3V Supply with 5V Tolerant I/O
JTAG Boundary Scan as per IEEE 1149.1
144-Pin eLQFP Package
APPLICATIONS
T1 Digital Cross-Connects
ATM and Frame Relay Equipment
Wireless Base Stations
ISDN Primary Rate Interface
E1/T1/J1 Multiplexer and Channel Banks
E1/T1/J1 LAN/WAN Routers
FUNCTIONAL DIAGRAM
Jtag
Software Control,
Hardware Control
and JTAG
MODESEL
RLOS
RTIP
RRING
TTTIP
TRING
Receiver
Transmitter
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
1
ORDERING INFORMATION
PART
8
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
144 eLQFP
144 eLQFP
144 eLQFP
144 eLQFP
DS26303L-XXX
DS26303L-XXX+
DS26303LN-XXX
DS26303LN-XXX+
DS26303
Note:
When XXX is 075, the part defaults to 75
Ω
impedance in E1
mode; when XXX is 120, the part defaults to 120
Ω
impedance.
+
Denotes a lead-free/RoHS-compliant package.
e = Exposed Pad.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 053107
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
TABLE OF CONTENTS
1
2
3
4
DETAILED DESCRIPTION ...............................................................................................................6
TELECOM SPECIFICATIONS COMPLIANCE.................................................................................7
BLOCK DIAGRAMS .........................................................................................................................9
PIN DESCRIPTION .........................................................................................................................11
4.1 H
ARDWARE AND
H
OST
P
ORT
O
PERATION
......................................................................................20
4.1.1
4.1.2
4.1.3
4.1.4
Hardware Mode................................................................................................................................... 20
Serial Port Operation .......................................................................................................................... 21
Parallel Port Operation........................................................................................................................ 22
Interrupt Handling ............................................................................................................................... 22
5
REGISTERS ....................................................................................................................................24
5.1 R
EGISTER
D
ESCRIPTION
...............................................................................................................29
5.1.1
5.1.2
5.1.3
5.1.4
Primary Registers................................................................................................................................ 29
Secondary Registers........................................................................................................................... 38
Individual LIU Registers ...................................................................................................................... 40
BERT Registers .................................................................................................................................. 47
6
FUNCTIONAL DESCRIPTION........................................................................................................54
6.1 P
OWER
-U
P AND
R
ESET
.................................................................................................................54
6.2 M
ASTER
C
LOCK
............................................................................................................................54
6.3 T
RANSMITTER
...............................................................................................................................55
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
Transmit Line Templates .................................................................................................................... 56
LIU Transmit Front-End ...................................................................................................................... 58
Dual-Rail Mode ................................................................................................................................... 59
Single-Rail Mode................................................................................................................................. 59
Zero Suppression—B8ZS or HDB3 .................................................................................................... 59
Transmit Power-Down ........................................................................................................................ 59
Transmit All Ones................................................................................................................................ 59
Driver Fail Monitor............................................................................................................................... 59
Peak Detector and Slicer .................................................................................................................... 59
Clock and Data Recovery ................................................................................................................... 59
Loss of Signal...................................................................................................................................... 60
AIS ...................................................................................................................................................... 60
Bipolar Violation and Excessive Zero Detector................................................................................... 62
LIU Receiver Front-End ...................................................................................................................... 62
6.4
R
ECEIVER
.....................................................................................................................................59
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.5
6.6
6.7
6.8
H
ITLESS
-P
ROTECTION
S
WITCHING
(HPS) ......................................................................................62
J
ITTER
A
TTENUATOR
.....................................................................................................................64
G.772 M
ONITOR
...........................................................................................................................65
L
OOPBACKS
..................................................................................................................................65
Analog Loopback ................................................................................................................................ 65
Digital Loopback.................................................................................................................................. 65
Remote Loopback............................................................................................................................... 66
Dual Loopback .................................................................................................................................... 67
Configuration and Monitoring.............................................................................................................. 68
BERT Interrupt Handling..................................................................................................................... 69
Receive Pattern Detection .................................................................................................................. 69
Transmit Pattern Generation............................................................................................................... 71
6.8.1
6.8.2
6.8.3
6.8.4
6.9
BERT...........................................................................................................................................68
6.9.1
6.9.2
6.9.3
6.9.4
7
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................................72
7.1 TAP C
ONTROLLER
S
TATE
M
ACHINE
..............................................................................................73
7.1.1
7.1.2
7.1.3
7.1.4
Test-Logic-Reset................................................................................................................................. 73
Run-Test-Idle ...................................................................................................................................... 73
Select-DR-Scan .................................................................................................................................. 73
Capture-DR ......................................................................................................................................... 73
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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.12
7.1.13
7.1.14
7.1.15
7.1.16
Shift-DR............................................................................................................................................... 73
Exit1-DR.............................................................................................................................................. 73
Pause-DR............................................................................................................................................ 73
Exit2-DR.............................................................................................................................................. 73
Update-DR .......................................................................................................................................... 73
Select-IR-Scan .................................................................................................................................... 74
Capture-IR........................................................................................................................................... 74
Shift-IR ................................................................................................................................................ 74
Exit1-IR ............................................................................................................................................... 74
Pause-IR ............................................................................................................................................. 74
Exit2-IR ............................................................................................................................................... 74
Update-IR............................................................................................................................................ 74
EXTEST .............................................................................................................................................. 76
HIGHZ ................................................................................................................................................. 76
CLAMP................................................................................................................................................ 76
SAMPLE/PRELOAD ........................................................................................................................... 76
IDCODE .............................................................................................................................................. 76
BYPASS.............................................................................................................................................. 76
Boundary Scan Register ..................................................................................................................... 77
Bypass Register .................................................................................................................................. 77
Identification Register ......................................................................................................................... 77
7.2
I
NSTRUCTION
R
EGISTER
................................................................................................................76
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.3
T
EST
R
EGISTERS
..........................................................................................................................77
7.3.1
7.3.2
7.3.3
8
9
10
OPERATING PARAMETERS .........................................................................................................78
THERMAL CHARACTERISTICS....................................................................................................79
AC CHARACTERISTICS ................................................................................................................80
10.1 L
INE
I
NTERFACE
C
HARACTERISTICS
...............................................................................................80
10.2 P
ARALLEL
H
OST
I
NTERFACE
T
IMING
C
HARACTERISTICS
.................................................................81
10.3 S
ERIAL
P
ORT
................................................................................................................................93
10.4 S
YSTEM
T
IMING
............................................................................................................................94
10.5 JTAG T
IMING
................................................................................................................................96
11 PIN CONFIGURATION ...................................................................................................................97
11.1 144-P
IN
LQFP
WITH
E
XPOSED
P
AD
..............................................................................................97
12 PACKAGE INFORMATION ............................................................................................................98
12.1 144-P
IN
LQFP
WITH
E
XPOSED
P
AD
P
ACKAGE
O
UTLINE
(56-G6037-002) (S
HEET
1
OF
2) ..............98
12.2 144-P
IN
LQFP
WITH
E
XPOSED
P
AD
P
ACKAGE
O
UTLINE
(S
HEET
2
OF
2).........................................99
13 DOCUMENT REVISION HISTORY...............................................................................................100
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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
LIST OF FIGURES
Figure 3-1. Block Diagram ........................................................................................................................................... 9
Figure 3-2. Receive Logic Detail................................................................................................................................ 10
Figure 3-3. Transmit Logic Detail............................................................................................................................... 10
Figure 4-1. 144-Pin eLQFP Pin Assignment ............................................................................................................. 19
Figure 4-2. Serial Port Operation for Write Access ................................................................................................... 21
Figure 4-3. Serial Port Operation for Read Access with CLKE = 0 ........................................................................... 21
Figure 4-4. Serial Port Operation for Read Access with CLKE = 1 ........................................................................... 22
Figure 4-5. Interrupt Handling Flow Diagram ............................................................................................................ 23
Figure 6-1. Prescaler PLL and Clock Generator ....................................................................................................... 54
Figure 6-2. T1 Transmit Pulse Templates ................................................................................................................. 56
Figure 6-3. E1 Transmit Pulse Templates ................................................................................................................. 57
Figure 6-4. LIU Front-End.......................................................................................................................................... 58
Figure 6-5. HPS Logic ............................................................................................................................................... 63
Figure 6-6. HPS Block Diagram................................................................................................................................. 63
Figure 6-7. Jitter Attenuation ..................................................................................................................................... 64
Figure 6-8. Analog Loopback..................................................................................................................................... 65
Figure 6-9. Digital Loopback...................................................................................................................................... 66
Figure 6-10. Remote Loopback ................................................................................................................................. 66
Figure 6-11. Dual Loopback ...................................................................................................................................... 67
Figure 6-12. PRBS Synchronization State Diagram.................................................................................................. 70
Figure 6-13. Repetitive Pattern Synchronization State Diagram............................................................................... 71
Figure 7-1. JTAG Functional Block Diagram ............................................................................................................. 72
Figure 7-2. TAP Controller State Diagram................................................................................................................. 75
Figure 10-1. Intel Nonmuxed Read Cycle ................................................................................................................. 82
Figure 10-2. Intel Mux Read Cycle ............................................................................................................................ 83
Figure 10-3. Intel Nonmux Write Cycle...................................................................................................................... 85
Figure 10-4. Intel Mux Write Cycle ............................................................................................................................ 86
Figure 10-5. Motorola Nonmux Read Cycle .............................................................................................................. 88
Figure 10-6. Motorola Mux Read Cycle..................................................................................................................... 89
Figure 10-7. Motorola Nonmux Write Cycle .............................................................................................................. 91
Figure 10-8. Motorola Mux Write Cycle ..................................................................................................................... 92
Figure 10-9. Serial Bus Timing Write Operation........................................................................................................ 93
Figure 10-10. Serial Bus Timing Read Operation with CLKE = 0.............................................................................. 93
Figure 10-11. Serial Bus Timing Read Operation with CLKE = 1.............................................................................. 93
Figure 10-12. Transmitter Systems Timing ............................................................................................................... 94
Figure 10-13. Receiver Systems Timing ................................................................................................................... 95
Figure 10-14. JTAG Timing ....................................................................................................................................... 96
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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
LIST OF TABLES
Table 2-1. T1-Related Telecommunications Specifications ........................................................................................ 7
Table 2-2. E1-Related Telecommunications Specifications ........................................................................................ 8
Table 4-1. Pin Descriptions........................................................................................................................................ 11
Table 4-2. Hardware Mode Configuration Examples................................................................................................. 20
Table 4-3. Parallel Port Mode Selection and Pin Functions ...................................................................................... 22
Table 5-1. Primary Register Set ................................................................................................................................ 24
Table 5-2. Secondary Register Set............................................................................................................................ 25
Table 5-3. Individual LIU Register Set....................................................................................................................... 25
Table 5-4. BERT Register Set ................................................................................................................................... 26
Table 5-5. Primary Register Set Bit Map ................................................................................................................... 27
Table 5-6. Secondary Register Set Bit Map .............................................................................................................. 27
Table 5-7. Individual LIU Register Set Bit Map.......................................................................................................... 28
Table 5-8. BERT Register Bit Map ............................................................................................................................ 28
Table 5-9. G.772 Monitoring Control ......................................................................................................................... 32
Table 5-10. TST Template Select Transceiver Register ........................................................................................... 35
Table 5-11. Template Selection................................................................................................................................. 35
Table 5-12. Address Pointer for Bank Selection........................................................................................................ 37
Table 5-13. MCLK Selections .................................................................................................................................... 42
Table 5-14. Jitter Attenuator Bandwidth Selections................................................................................................... 43
Table 5-15. PLL Clock Select .................................................................................................................................... 45
Table 5-16. Clock A Select ........................................................................................................................................ 45
Table 6-1. Telecommunications Specification Compliance for DS26303 Transmitters ............................................ 55
Table 6-2. Registers Related to Control of DS26303 Transmitters ........................................................................... 55
Table 6-3. DS26303 Template Selections................................................................................................................. 56
Table 6-4. LIU Front-End Values ............................................................................................................................... 58
Table 6-5. Loss Criteria T1.231, G.775, and ETS 300 233 Specifications................................................................ 60
Table 6-6. AIS Criteria T1.231, G.775, and ETS 300 233 Specifications.................................................................. 61
Table 6-7. AIS Detection and Reset Criteria ............................................................................................................. 61
Table 6-8. Registers Related to AIS Detection.......................................................................................................... 61
Table 6-9. BPV, Code Violation, and Excessive Zero Error Reporting ..................................................................... 62
Table 6-10. Pseudorandom Pattern Generation........................................................................................................ 68
Table 6-11. Repetitive Pattern Generation ................................................................................................................ 68
Table 7-1. Instruction Codes for IEEE 1149.1 Architecture....................................................................................... 76
Table 7-2. ID Code Structure..................................................................................................................................... 77
Table 7-3 Device ID Codes........................................................................................................................................ 77
Table 8-1. Recommended DC Operating Conditions ................................................................................................ 78
Table 8-2. Capacitance.............................................................................................................................................. 78
Table 8-3. DC Characteristics.................................................................................................................................... 78
Table 9-1. Thermal Characteristics............................................................................................................................ 79
Table 10-1. Transmitter Characteristics..................................................................................................................... 80
Table 10-2. Receiver Characteristics......................................................................................................................... 80
Table 10-3. Intel Read Mode Characteristics ............................................................................................................ 81
Table 10-4. Intel Write Cycle Characteristics ............................................................................................................ 84
Table 10-5. Motorola Read Cycle Characteristics ..................................................................................................... 87
Table 10-6. Motorola Write Cycle Characteristics ..................................................................................................... 90
Table 10-7. Serial Port Timing Characteristics .......................................................................................................... 93
Table 10-8. Transmitter System Timing .................................................................................................................... 94
Table 10-9. Receiver System Timing......................................................................................................................... 95
Table 10-10. JTAG Timing Characteristics................................................................................................................ 96
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