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Datasheet> All Categories > logic> logic> MC74HCT373ANG
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MC74HCT373ANG

Description
Latches 5V Octal D-Type
Categorylogic    logic   
File Size152KB，9 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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MC74HCT373ANG Overview

Latches 5V Octal D-Type

MC74HCT373ANG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerON Semiconductor
Parts packaging codeDIP
package instructionDIP, DIP20,.3
Contacts20
Reach Compliance Codeunknown
seriesHCT
JESD-30 codeR-PDIP-T20
JESD-609 codee3
length26.415 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.006 A
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP20,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)260
power supply5 V
Prop。Delay @ Nom-Sup42 ns
propagation delay (tpd)48 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width7.62 mm

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Download Datasheet
MC74HCT373A
Octal 3-State Noninverting
Transparent Latch with
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to High−Speed CMOS inputs.
The HCT373A is identical in pinout to the LS373.
The eight latches of the HCT373A are transparent D−type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs.
When Latch Enable is taken low, data meeting the setup and hold
times becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high−impedance
state. Thus, data may be latched even when the outputs are not
enabled.
The HCT373A is identical in function to the HCT573A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT533A, which has
inverting outputs.
•
Output Drive Capability: 15 LSTTL Loads
•
TTL/NMOS−Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0
mA
•
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
•
Chip Complexity: 196 FETs or 49 Equivalent Gates
•
These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
MARKING
DIAGRAMS
20
PDIP−20
N SUFFIX
CASE 738
20
MC74HCT373AN
AWLYYWWG
1
20
20
1
SOIC−20
DW SUFFIX
CASE 751D
1
20
20
1
TSSOP−20
DT SUFFIX
CASE 948E
1
20
SOEIAJ−20
F SUFFIX
CASE 967
1
A
WL, L
YY, Y
WW, W
G or
G
HCT
373A
ALYWG
G
HCT373A
AWLYYWWG
1
20
1
74HCT373A
AWLYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
MC74HCT373ANG
MC74HCT373ADWG
MC74HCT373ADWR2G
MC74HCT373AFELG
MC74HCT373ADTR2G
Package
PDIP−20
SOIC−20
SOIC−20
Shipping
†
18 / Box
38 / Rail
1000 / Reel
SOEIAJ−20 2000 / Reel
TSSOP−20 2500 / Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2011
June, 2011
−
Rev. 12
1
Publication Order Number:
MC74HCT373A/D

MC74HCT373ANG Related Products

MC74HCT373ANG MC74HCT373AFEL MC74HCT373AN
Description Latches 5V Octal D-Type Latches 5V Octal D-Type Latches 5V Octal D-Type
Is it Rohs certified? conform to - incompatible
Maker ON Semiconductor - ON Semiconductor
Parts packaging code DIP - DIP
package instruction DIP, DIP20,.3 - DIP, DIP20,.3
Contacts 20 - 20
Reach Compliance Code unknown - not_compliant
series HCT - HCT
JESD-30 code R-PDIP-T20 - R-PDIP-T20
JESD-609 code e3 - e0
length 26.415 mm - 26.415 mm
Load capacitance (CL) 50 pF - 50 pF
Logic integrated circuit type BUS DRIVER - BUS DRIVER
MaximumI(ol) 0.006 A - 0.006 A
Number of digits 8 - 8
Number of functions 1 - 1
Number of ports 2 - 2
Number of terminals 20 - 20
Maximum operating temperature 125 °C - 125 °C
Minimum operating temperature -55 °C - -55 °C
Output characteristics 3-STATE - 3-STATE
Output polarity TRUE - TRUE
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code DIP - DIP
Encapsulate equivalent code DIP20,.3 - DIP20,.3
Package shape RECTANGULAR - RECTANGULAR
Package form IN-LINE - IN-LINE
Peak Reflow Temperature (Celsius) 260 - NOT SPECIFIED
power supply 5 V - 5 V
Prop。Delay @ Nom-Sup 42 ns - 42 ns
propagation delay (tpd) 48 ns - 48 ns
Certification status Not Qualified - Not Qualified
Maximum seat height 4.57 mm - 4.57 mm
Maximum supply voltage (Vsup) 5.5 V - 5.5 V
Minimum supply voltage (Vsup) 4.5 V - 4.5 V
Nominal supply voltage (Vsup) 5 V - 5 V
surface mount NO - NO
technology CMOS - CMOS
Temperature level MILITARY - MILITARY
Terminal surface Matte Tin (Sn) - annealed - Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE - THROUGH-HOLE
Terminal pitch 2.54 mm - 2.54 mm
Terminal location DUAL - DUAL
Maximum time at peak reflow temperature 40 - NOT SPECIFIED
width 7.62 mm - 7.62 mm

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