IS63LV1024
IS63LV1024L
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
FEATURES
• High-speed access times:
8, 10, 12 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with
CE
and
OE
options
•
CE
power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 32-pin 300-mil SOJ
– 32-pin 400-mil SOJ
– 32-pin TSOP (Type II)
– 32-pin STSOP (Type I)
– 36-pin BGA (8mmx10mm)
• Lead-free Available
MAY 2012
DESCRIPTION
The ISSI IS63LV1024/IS63LV1024L is a very high-speed,
low power, 131,072-word by 8-bit CMOS static RAM in
revolutionary pinout. The IS63LV1024/IS63LV1024L is fab-
ricated using ISSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields higher performance and low
power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS63LV1024/IS63LV1024L operates from a single 3.3V
power supply and all inputs are TTL-compatible.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K X 8
MEMORY ARRAY
VDD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. P
05/09/2012
1
IS63LV1024
IS63LV1024L
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O Operation
High-Z
High-Z
D
OUT
D
IN
V
DD
Current
I
SB
1
, I
SB
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
Value
–0.5 to V
DD
+ 0.5
–65 to +150
1.0
Unit
V
°
C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
DD
3.3V ± 0.3V
3.3V ± 0.15V
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
DD
GND
≤
V
OUT
≤
V
DD
, Outputs Disabled
Com.
Ind.
Com.
Ind.
Test Conditions
V
DD
= Min., I
OH
= –4.0 mA
V
DD
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.2
–0.3
–1
–5
–1
–5
Max.
—
0.4
V
DD
+ 0.3
0.8
1
5
1
5
Unit
V
V
V
V
µA
µA
Note:
1. V
IL
(min.) = –0.3V DC; V
IL
(min.) = –2.0V AC (pulse width under Vss < 5ns). Not 100% tested.
V
IH
(max.) = V
DD
+ 0.3V DC; V
IH
(max.) = V
DD
+ 2.0V AC (pulse width over V
DD
< 5ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. P
05/09/2012
3
IS63LV1024
IS63LV1024L
IS63LV1024 POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
1
V
DD
Operating
Supply Current
Test Conditions
V
DD
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = Max.
Com.
Ind.
typ.
(2)
Ind. (@15 ns)
Com.
Ind.
Com.
Ind.
Com.
Ind.
typ.
(2)
-8 ns
Min. Max.
—
—
—
—
—
—
—
—
—
—
160
170
105
55
55
25
30
5
10
0.5
-10 ns
Min. Max.
—
—
—
—
—
—
—
—
—
—
150
160
95
45
45
25
30
5
10
0.5
-12 ns
Min. Max.
—
—
—
—
—
—
—
—
—
—
—
130
140
75
90
40
40
25
30
5
10
0.5
Unit
mA
I
SB
TTL Standby
Current
(TTL Inputs)
TTL Standby
Current
(TTL Inputs)
CMOS Standby
Current
(CMOS Inputs)
V
DD
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = Max
V
DD
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
DD
= Max.,
CE
≥
V
DD
– 0.2V,
V
IN
≥
V
DD
– 0.2V, or
V
IN
≤
0.2V, f = 0
mA
I
SB
1
mA
I
SB
2
mA
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
= 3.3V, T
A
= 25
o
C. Not 100% tested.
IS63LV1024L POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
1
V
DD
Operating
Supply Current
TTL Standby
Current
(TTL Inputs)
TTL Standby
Current
(TTL Inputs)
CMOS Standby
Current
(CMOS Inputs)
Test Conditions
V
DD
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = Max.
V
DD
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = Max
V
DD
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
DD
= Max.,
CE
≥
V
DD
– 0.2V,
V
IN
≥
V
DD
– 0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
typ.
(2)
Com.
Ind.
Com.
Ind.
Com.
Ind.
typ.
(2)
-8 ns
Min. Max.
—
—
—
—
—
—
—
—
—
—
100
110
75
35
40
15
20
1
1.5
0.05
-10 ns
Min. Max.
—
—
—
—
—
—
—
—
—
—
95
105
70
30
35
15
20
1
1.5
0.05
-12 ns
Min. Max.
—
—
—
—
—
—
—
—
—
—
90
100
65
25
30
15
20
1
1.5
0.05
Unit
mA
I
SB
mA
I
SB
1
mA
I
SB
2
mA
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
= 3.3V, T
A
= 25
o
C. Not 100% tested.
CAPACITANCE
(1,2)
Symbol
C
IN
C
I/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, V
DD
= 3.3V.
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. P
05/09/2012
IS63LV1024
IS63LV1024L
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
OE
to Low-Z Output
OE
to High-Z Output
CE
to Low-Z Output
CE
to High-Z Output
CE
to Power Up Time
CE
to Power Down Time
-8 ns
Min.
Max.
8
—
2
—
—
0
0
3
0
0
—
—
8
—
8
4
—
4
—
4
—
8
-10 ns
Min.
Max.
10
—
2
—
—
0
0
3
0
0
—
—
10
—
10
5
—
5
—
5
—
10
-12 ns
Min.
Max.
12
—
2
—
—
0
0
3
0
0
—
—
12
—
12
6
—
6
—
6
—
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
t
PU
t
PD
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
loading specified in Figure 1.
2. Tested with the loading specified in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
317
Ω
Z
OUT
= 50
Ω
OUTPUT
50
Ω
V
T
= 1.5V
Figure 1
Figure 2
3.3V
OUTPUT
5 pF
Including
jig and
scope
351
Ω
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. P
05/09/2012
5
DSP and ARM Processors
京公网安备 11010802033920号
EEWORLD
