849N202CKI-018LFT datasheet, PDF

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849N202CKI-018LFT: DescriptionClock Synthesizer / Jitter Cleaner JITTER ATTENUATOR; Categorysemiconductor Analog mixed-signal IC; File Size1MB，40 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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849N202CKI-018LFT Overview

Clock Synthesizer / Jitter Cleaner JITTER ATTENUATOR

849N202CKI-018LFT Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	IDT (Integrated Device Technology, Inc.)
Product Category	Clock Synthesizer / Jitter Cleaner
RoHS	Details
Packaging	Reel
Factory Pack Quantity	5000

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FemtoClock

NG Universal Frequency

Translator

849N202

Datasheet

General Description

The 849N202 is a highly flexible FemtoClock® NG general purpose,

low phase noise Universal Frequency Translator / Synthesizer with

alarm and monitoring functions suitable for networking and

communications applications. It is able to generate any output

frequency in the 0.98MHz - 312.5MHz range and most output

frequencies in the 312.5MHz - 1,300MHz range (see Table 3 for

details). A wide range of input reference clocks and a range of

low-cost fundamental mode crystal frequencies may be used as the

source for the output frequency.

The 849N202 has three operating modes to support a very broad

spectrum of applications:

1) Frequency Synthesizer

Features

•

generation FemtoClock® NG technology

Universal Frequency Translator (UFT) / Frequency Synthesizer

Two outputs, individually programmable as LVPECL or LVDS

•

Both outputs may be set to use 2.5V or 3.3V output levels

Programmable output frequency: 0.98MHz up to 1,300MHz

Zero ppm frequency translation

Two differential inputs support the following input types:

LVPECL, LVDS, LVHSTL, HCSL

Input frequency range: 8kHz - 710MHz

Crystal input frequency range: 16MHz - 40MHz

Two factory-set register configurations for power-up default state

•

Synthesizes output frequencies from a 16MHz - 40MHz

fundamental mode crystal.

Fractional feedback division is used, so there are no

requirements for any specific crystal frequency to produce the

desired output frequency with a high degree of accuracy.

Applications: PCI Express, Computing, General Purpose

Translates any input clock in the 16MHz - 710MHz frequency

range into any supported output frequency.

This mode has a high PLL loop bandwidth in order to track input

reference changes, such as Spread-Spectrum Clock

modulation, so it will not attenuate much jitter on the input

reference.

Applications: Networking & Communications.

Translates any input clock in the 8kHz -710MHz frequency

range into any supported output frequency.

This mode supports PLL loop bandwidths in the 10Hz - 580Hz

range and makes use of an external crystal to provide

significant jitter attenuation.

2) High-Bandwidth Frequency Translator

•

Power-up default configuration pin or register selectable

Configurations customized via One-Time Programmable ROM

Settings may be overwritten after power-up via I

C Serial interface for register programming

RMS phase jitter at 125MHz, using a 40MHz crystal

(12kHz - 20MHz): 510fs (typical), Low Bandwidth Mode (FracN)

RMS phase jitter at 400MHz, using a 40MHz crystal

(12kHz - 40MHz): 321fs (typical), Synthesizer Mode (Integer FB)

Output supply voltage modes:

CCA

CCO

3.3V/3.3V/3.3V

3.3V/3.3V/2.5V (LVPECL only)

2.5V/2.5V/2.5V

-40°C to 85°C ambient operating temperature

Available in lead-free (RoHS 6) package

3) Low-Bandwidth Frequency Translator

•

This device provides two factory-programmed default power-up

configurations burned into One-Time Programmable (OTP) memory.

The configuration to be used is selected by the CONFIG pin. The two

configurations are specified by the customer and are programmed by

IDT during the final test phase from an on-hand stock of blank

devices. The two configurations may be completely independent of

one another.

One usage example might be to install the device on a line card with

two optional daughter cards: an OC-12 option requiring a 622.08MHz

LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet

option requiring a 125MHz LVPECL clock translated from the same

19.44MHz input reference.

To implement other configurations, these power-up default settings

can be overwritten after power-up using the I

C interface and the

device can be completely reconfigured. However, these settings

would have to be re-written next time the device powers-up.

XTALBAD

CLK1BAD

CCA

XTAL_IN

XTAL_OUT

CLK_SEL

CLK0

nCLK0

CLK1

nCLK1

40 39 38 37 36 35 34 33 32 31

CLK_ACTIVE

HOLDOVER

Pin Assignment

CLK0BAD

LF1

LF0

LOCK_IND

OE0

nQ0

CCO

nQ1

OE1

849N202

40 Lead VFQFN

6mm x 6mm x 0.925mm

K Package

Top View

11 12 13 14 15 16 17 18 19 20

CONFIG

S_A1

S_A0

PLL_BYPASS

SDATA

SCLK

Revision B, May 20, 2016

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