ADM6926
26 port 10/100 Mbps Ethernet Switch
Controller
Version 1.0
ADMtek
.
com.tw
Information in this document is provided in connection with ADMtek products. ADMtek may make
changes to specifications and product descriptions at any time, without notice. Designers must not rely on
the absence or characteristics of any features or instructions marked “reserved” or “undefined”. ADMtek
reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them
The products may contain design defects or errors know as errata, which may cause the product to deviate
from published specifications. Current characterized errata are available on request. To obtain latest
documentation please contact you local ADMtek sales office or visit ADMtek’s website at
http://www.ADMtek.com.tw
*Third-party brands and names are the property of their respective owners.
ADMtek Inc.
V1.0
About this Manual
General Release
Intended Audience
ADMtek’s Customers
Structure
This Data sheet contains 5 chapters
Chapter 1
Chapter 2
Chapter 3
Chapter 4.
Chapter 5.
Product Overview
Interface Description
Function Description
Electrical Specification
Packaging
Revision History
Date
Version
08 Aug 2003
1.0
Change
1. First release of ADM6926
Customer Support
ADMtek Incorporated,
2F, No.2, Li-Hsin Rd.,
Science-based Industrial Park,
Hsinchu, 300, Taiwan, R.O.C.
Sales Information
Tel + 886-3-5788879
Fax + 886-3-5788871
ADMtek Inc.
V1.0
Table of Contents
Chapter 1 Product Overview ........................................................................................ 1-1
1.1
Overview.......................................................................................................... 1-1
1.2
Features ............................................................................................................ 1-1
1.3
Block Diagram ................................................................................................. 1-2
1.4
Abbreviations................................................................................................... 1-3
1.5
Conventions ..................................................................................................... 1-4
1.5.1
Data Lengths............................................................................................ 1-4
1.5.2
Register Type Descriptions ...................................................................... 1-4
1.5.3
Pin Type Descriptions.............................................................................. 1-4
Chapter 2 Interface Description ................................................................................... 2-1
2.1 Pin Diagram – ADM6926 (SS-SMII Interface)..................................................... 2-1
2.2
Pin Description................................................................................................. 2-2
2.2.1
SS-SMII Networking Interface, 60 pins ................................................... 2-2
2.2.2
MII/RMII Interface, 28pins...................................................................... 2-3
2.2.3
Power/Ground.......................................................................................... 2-5
2.2.4
Miscellaneous pins, 16 pins ..................................................................... 2-5
Chapter 3 Function Description ................................................................................... 3-1
3.1.1
Basic Operation ....................................................................................... 3-1
3.1.2
Address Learning ..................................................................................... 3-1
3.1.3
Address Aging .......................................................................................... 3-2
3.1.4
Address Recognition and Packet Forwarding ......................................... 3-3
3.1.5
Trunking Port Forwarding ...................................................................... 3-4
3.1.6
Illegal Frames.......................................................................................... 3-4
3.1.7
Back off Algorithm ................................................................................... 3-4
3.1.8
Buffers and Queues .................................................................................. 3-4
3.1.9
Half Duplex Flow Control ....................................................................... 3-5
3.1.10
Full Duplex Flow Control........................................................................ 3-5
3.1.11
Inter-Packet Gap (IPG) ........................................................................... 3-5
3.1.13
Priority Control ....................................................................................... 3-6
3.1.14
Alert LED Display.................................................................................... 3-7
3.1.15
Broadcast Storm Filter ............................................................................ 3-7
3.1.16
Collision LED Display............................................................................. 3-7
3.1.17
Bandwidth Control................................................................................... 3-8
3.1.18
Smart Discard .......................................................................................... 3-8
3.1.19
Security Support....................................................................................... 3-8
3.1.20
Smart Counter Support ............................................................................ 3-8
3.1.21
Length 1536 Mode ................................................................................... 3-8
3.1.22
PHY Management (MDC/MDIO Interface)............................................. 3-8
3.1.23
Forward Special Packets to the CPU Port .............................................. 3-9
3.1.24
Special TAG ........................................................................................... 3-10
3.1.25
Port 24 and Port 25 Interface (Only SS-SMII package support)........... 3-12
3.1.26
Hardware, EEPROM and SMI Interface for Configuration.................. 3-13
3.2
EEPROM Register Format ............................................................................ 3-17
3.2.1
Signature (Index: 0h) ............................................................................. 3-20
3.2.2
Global Configuration Register (Index: 1h)............................................ 3-20
ADM6926
i
ADMtek Inc.
V1.0
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
3.2.14
3.2.15
3.2.16
3.2.17
3.2.18
3.2.19
3.2.20
3.2.21
3.2.22
3.2.23
3.2.24
3.2.25
3.2.26
3.2.27
3.2.28
3.2.29
3.2.30
3.2.31
3.2.32
3.2.33
3.2.34
3.2.35
3.2.36
3.2.37
3.2.38
3.2.39
3.2.40
3.2.41
3.2.42
3.2.43
3.2.44
3.2.45
3.2.46
3.2.47
3.2.48
Port Configuration Registers (Index: 2h ~ 1bh).................................... 3-21
Miscellaneous Configuration (Index: 1ch) ............................................ 3-23
VLAN(TOS) Priority Map (Index: 1dh) ................................................. 3-23
Forwarding Group Outbound Port Map Low ....................................... 3-24
Forwarding Group Outbound Port Map High ...................................... 3-25
P0 VID and PVID Shift (Index: 5eh) ..................................................... 3-25
P1~P25 VID Configuration ................................................................... 3-26
P0, P1, P2, P3 Bandwidth Control Register (Index: 78h)..................... 3-26
P4, P5, P6, P7 Bandwidth Control Register (Index: 79h)..................... 3-27
P8, P9, P10, P11 Bandwidth Control Register (Index: 7ah)................. 3-27
P12, P13, P14, P15 Bandwidth Control Register (Index: 7bh)............. 3-28
P16, P17, P18, P19 Bandwidth Control Register (Index: 7ch) ............. 3-28
P20, P21, P22, P23 Bandwidth Control Register (Index: 7dh)............. 3-29
P24, P25 Bandwidth Control Register (Index: 7eh).............................. 3-29
Bandwidth Control Enable Register Low (Index: 7fh) .......................... 3-30
Bandwidth Control Enable Register High (Index: 80h) ........................ 3-30
Reserved Registers (Index: 81h~8ah) .................................................... 3-30
Customized PHY Control Group 0 (Index: 8bh).................................... 3-31
Customized PHY Control Group 1 (Index: 8ch).................................... 3-31
Customized PHY Control Group 2 (Index: 8dh).................................... 3-32
Customized PHY Control Group 3 (Index: 8eh).................................... 3-32
Group 0 PHY Customized DATA 0 (Index: 8fh).................................... 3-32
Group 0 PHY Customized DATA 1 (Index: 90h) ................................... 3-32
Group 1 PHY Customized DATA 0 (Index: 91h) ................................... 3-33
Group 1 PHY Customized DATA 1 (Index: 92h) ................................... 3-33
Group 2 PHY Customized DATA 0 (Index: 93h) ................................... 3-33
Group 2 PHY Customized DATA 1 (Index: 94h) ................................... 3-33
Group 3 PHY Customized DATA 0 (Index: 95h) ................................... 3-33
Group 3 PHY Customized DATA 1 (Index: 96h) ................................... 3-33
PHY Customized Enable Register (Index: 97h)..................................... 3-33
PPPOE Control Register0 (Index: 98h) ................................................ 3-34
PPPOE Control Register 1 (Index: 99h) ............................................... 3-34
PHY Control Register 0 (Index: 9ah) .................................................... 3-35
PHY Control Register 1 (Index: 9bh) .................................................... 3-35
Disable MDIO Active Register 0 (Index: 9ch)....................................... 3-36
Disable MDIO Active Register 1 (Index: 9dh) ...................................... 3-36
Port Disable Register 0 (Index: 9eh) ..................................................... 3-37
Port Disable Register 1 (Index: 9fh)...................................................... 3-37
IGMP Snooping Control Register 0 (Index: a0h).................................. 3-37
IGMP Snooping Control Register 1 (Index: a1h).................................. 3-38
CPU Control Register (Index: a2h)....................................................... 3-38
Special MAC Forward Control Register 0 (Index: a3h) ....................... 3-39
Special MAC Forward Control Register 2 (Index: a4h) ....................... 3-40
Special MAC Forward Control Register 2 (Index: a5h) ....................... 3-40
Trunking Enable Register 0 (Index: a6h) .............................................. 3-41
Trunking Enable Register 1 (Index: a7h) .............................................. 3-41
ADM6926
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ADMtek Inc.
3.3
Switch Register Map...................................................................................... 3-42
3.3.1
Version ID (Offset: 0h) .......................................................................... 3-42
3.3.2
Link Status (Offset: 1h) .......................................................................... 3-42
3.3.3
Speed Status (Offset: 2h)........................................................................ 3-43
3.3.4
Duplex Status (Offset: 3h)...................................................................... 3-44
3.3.5
Flow Control Status (Offset: 4h)............................................................ 3-44
3.3.6
Address Table Control and Status Register ........................................... 3-45
3.3.7
PHY Control Register (Offset: bh)......................................................... 3-51
3.3.8
Hardware Status (Offset: dh)................................................................. 3-51
3.3.9
Receive Packet Count Overflow (Offset: eh) ......................................... 3-52
3.3.10
Receive Packet Length Count Overflow (Offset: fh).............................. 3-53
3.3.11
Transmit Packet Count Overflow (Offset: 10h) ..................................... 3-53
3.3.12
Transmit Packet Length Count Overflow (Offset: 11h)......................... 3-54
3.3.13
Error Count Overflow (Offset: 12h) ...................................................... 3-54
3.3.14
Collision Count Overflow (Offset: 13h)................................................. 3-55
3.3.15
Renew Counter Register (Offset: 14h)................................................... 3-56
3.3.16
Read Counter Control & Status Register .............................................. 3-57
3.3.17
Reload MDIO Register (Offset: 17h)..................................................... 3-57
3.3.18
Spanning Tree Port State 0 (Offset: 18h) .............................................. 3-58
3.3.19
Spanning Tree Port State 1 (Offset: 19h) .............................................. 3-58
3.3.20
Source Port Register (Offset: 1ah) ........................................................ 3-59
3.3.21
Transmit Port Register (Offset: 1bh) ..................................................... 3-59
3.3.22
Counter Register: Offset Hex. 0100h ~ 019b......................................... 3-59
Chapter 4 Electrical Specification................................................................................ 4-1
4.1
DC Characterization......................................................................................... 4-1
4.1.1
Absolute Maximum Rating....................................................................... 4-1
4.1.2
Recommended Operating Conditions ...................................................... 4-1
4.1.3
DC Electrical Characteristics for 3.3V Operation .................................. 4-1
4.2
AC Characterization......................................................................................... 4-2
4.2.1
XI/OSCI (Crystal/Oscillator) Timing....................................................... 4-2
4.2.1
Power On Reset........................................................................................ 4-2
4.2.2
EEPROM Interface Timing...................................................................... 4-3
4.2.3
10Base-TX MII Output Timing ................................................................ 4-3
4.2.4
10Base-TX MII Input Timing ................................................................... 4-4
4.2.5
100Base-TX MII Output Timing .............................................................. 4-5
4.2.6
100Base-TX MII Input Timing ................................................................. 4-5
4.2.7
Reduced MII Timing ................................................................................ 4-6
4.2.8
SS_SMII Transmit Timing........................................................................ 4-7
4.2.9
SS_SMII Receive Timing.......................................................................... 4-7
4.2.10
Serial Management Interface (MDC/MDIO) Timing .............................. 4-8
Chapter 5 Packaging...................................................................................................... 5-1
V1.0
ADM6926
iii
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