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ASM5I2308AG-1-16-TT

Description
PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, GREEN, TSSOP-16
Categorylogic    logic   
File Size376KB,17 Pages
ManufacturerPulseCore Semiconductor Corporation
Environmental Compliance
Download Datasheet Parametric View All

ASM5I2308AG-1-16-TT Overview

PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, GREEN, TSSOP-16

ASM5I2308AG-1-16-TT Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
package instructionTSSOP,
Reach Compliance Codeunknown
series2308
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G16
length5 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.2 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
minfmax133 MHz
Base Number Matches1
November 2006
rev 1.5
3.3V Zero-Delay Buffer
General Features
Zero input - output propagation delay, adjustable by
capacitive load on FBK input.
Multiple configurations - Refer “ASM5P2308A
Configurations “ Table.
Input frequency range: 15MHz to 133MHz
Multiple low-skew outputs.
Output-output skew less than 200 pS.
Device-device skew less than 700 pS.
Two banks of four outputs, three-stateable by two
select inputs.
Less than 200 pS cycle-to-cycle jitter
(-1, -1H, -2, -3, -4, -5H).
Available in 16-pin SOIC and TSSOP packages.
3.3V operation.
Advanced 0.35µ CMOS technology.
Industrial temperature available.
The
ASM5P2308A
is
ASM5P2308A
the Select Input Decoding Table. If all the output clocks are
not required, Bank B can be three-stated. The select input
also allows the input clock to be directly applied to the
outputs for chip and system testing purposes.
Multiple ASM5P2308A devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
700 pS.
available
in
five
different
configurations(Refer “ASM5P2308A Configurations” Table).
The ASM5P2308A-1 is the base part, where the output
frequencies equal the reference if there is no counter in the
feedback path. The ASM5P2308A-1H is the high-drive
version of the -1 and the rise and fall times on this device
are much faster.
Functional Description
ASM5P2308A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It is available in a
16-pin package. The part has an on-chip PLL which locks
to an input clock presented on the REF pin. The PLL
feedback is required to be driven to FBK pin, and can be
obtained from one of the outputs. The input-to-input
propagation delay is guaranteed to be less than 350 pS,
and the output-to-output skew is guaranteed to be less than
250 pS.
The ASM5P2308A-2 allows the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration
and output frequencies depends on which output drives the
feedback pin. The ASM5P2308A-3 allows the user to
obtain 4X and 2X frequencies on the outputs.
The ASM5P2308A-4 enables the user to obtain 2X clocks
on all outputs.
The ASM5P2308A-5H is a high-drive version with REF/2
on both banks. Thus, the part is extremely versatile, and
The ASM5P2308A has two banks of four outputs each,
which can be controlled by the select inputs as shown in
can be used in a variety of applications.
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
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