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GS71024GT-12I

Description
Standard SRAM, 64KX24, 12ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
Categorystorage    storage   
File Size659KB,14 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Environmental Compliance
Download Datasheet Parametric View All

GS71024GT-12I Overview

Standard SRAM, 64KX24, 12ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

GS71024GT-12I Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerGSI Technology
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time12 ns
JESD-30 codeR-PQFP-G100
JESD-609 codee3
length20 mm
memory density1572864 bit
Memory IC TypeSTANDARD SRAM
memory width24
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize64KX24
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfacePURE MATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
Base Number Matches1
GS71024T/U
TQFP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 8, 9, 10, 12, 15 ns
• CMOS low power operation: 190/170/160/130/110 mA at
minimum cycle time.
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40 to 85°C
• Package
T: 100-pin TQFP package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array
GT: RoHS-compliant 100-pin TQFP available
GU: RoHS-compliant 6 mm x 8 mm Fine Pitch BGA
64K x 24
1.5Mb Asynchronous SRAM
1
A
B
C
D
E
F
G
H
2
3
4
8, 9, 10, 12, 15 ns
3.3 V V
DD
Center V
DD
and V
SS
Fine Pitch BGA Bump Configuration
5
6
DQ
DQ
DQ
V
SS
V
DD
DQ
DQ
DQ
A
3
DQ
DQ
DQ
DQ
DQ
DQ
A
15
A
2
CE2
CE1
A
5
A
7
A
9
A
11
A
14
A
1
WE
OE
A
4
A
6
A
8
A
10
A
13
A
0
DQ
DQ
DQ
DQ
DQ
DQ
A
12
DQ
DQ
DQ
V
DD
V
SS
DQ
DQ
DQ
Description
The GS71024 is a high speed CMOS static RAM organized as
65,536 words by 24 bits. Static design eliminates the need for
external clocks or timing strobes. The GS71024 operates on a
single 3.3 V power supply, and all inputs and outputs are TTL-
compatible. The GS71024 is available in a 6 mm x 8 mm Fine
Pitch BGA package, as well as in a 100-pin TQFP package.
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Pin Descriptions
Symbol
A
0
to A
15
X/Y
WE
CE1, CE2
V
DD
Description
Address input
Vector Input
Write enable input
Chip enable input
+3.3 V power supply
Symbol
DQ
1
to DQ
24
V/S
OE
V
SS
Description
Data input/output
Address Multiplexer Control
Output enable input
Ground
Block Diagram
A0
Row
Decoder
Address
Input
A14
A15
X/Y
V/S
CE1
CE2
WE
OE
Memory Array
1024 x 1536
0
1
Q
Column
Decoder
Control
I/O Buffer
DQ1
DQ24
Rev: 1.06 8/2005
1/14
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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