EDI8F8257C
256Kx8 Static RAM CMOS, Module
FEATURES
256Kx8 bit CMOS Static
Random Access Memory
Access Times 70, 85 and 100ns
Data Retention Function (LP version)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
High Density Packaging
DESCRIPTION
The EDI8F8257C is a 2Mb CMOS Static RAM based on two
128Kx8 Static RAMs mounted on a multi-layered epoxy laminate
(FR4) substrate.
Functional equivalence to the monolithic 2Mb Static RAM is
achieved by utilization of an on-board decoder that interprets the
higher order address (A17) to select one of the 128Kx8 Static
RAMs.
The 32 pin DIP pinout adheres to the JEDEC standard for the two
megabit device, to ensure compatibility with future monolithics.
The device is available with Low Power and Data Retention
(EDI8F8257LP).
All inputs and outputs are TTL compatible and operate from a
single 5V supply. Fully asynchronous, the EDI8F8257C requires
no clocks or refreshing for operation.
32 Pin SOIC Module, No. 21 (OBSOLETE)
32 Pin DIP Module, No. 184
Single +5V (±10%) Supply Operation
PIN CONFIGURATIONS AND BLOCK DIAGRAM
OT
N
NS
SIG
DE
EW
RN
FO
ED
ND
ME
OM
EC
R
PIN NAMES
Address Inputs
Chip Enable
Write Enable
AØ-A17
E
W
G
DQØ-DQ7
VCC
VSS
NC
Output Enable
Common Data Input/Output
Power (+5V±10%)
Ground
No Connection
Sept. 2001 Rev. 9
ECO #14605
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI8F8257C
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Industrial
Storage Temperature
Plastic
Power Dissipation
Output Current
-0.5V to 7.0V
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
1 Watt
20 mA
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Sym
VCC
VSS
VIH
VIL
Min
4.5
0
2.2
-0.3
Typ
5.0
0
--
--
Max
5.5
0
6.0
0.8
Units
V
V
V
V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
VSS to 3.0V
5ns
1.5V
1TTL, CL =100pF
DC ELECTRICAL CHARACTERISTICS
Parameter
Operating Power
Supply Current
Standby (TTL) Power
Supply Current
Full Standby Power
Supply Current (CMOS)
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
*Typical: TA = 25°C, VCC = 5.0V
Sym
ICC1
ICC2
ICC3
ILI
ILO
VOH
VOL
Conditions
W, E = VIL, II/O = 0mA,
Min Cycle
E
³
VIH, VIN
£
VIL
VIN
³
VIH
E
³
VCC-0.2V
VIN
³
VCC-0.2V
VIN
£
0.2V
VIN = 0V to VCC
V I/O = 0V to VCC
IOH = -1.0mA
IOL = 2.1mA
Min
--
--
C
LP
--
--
-10
-10
2.4
--
Typ*
110
10
2
40
--
--
--
--
Max
130
35
5
400
10
10
--
0.4
Units
mA
mA
mA
µA
µA
µA
V
V
CAPACITANCE
TRUTH TABLE
G
X
H
L
X
E
H
L
L
L
W
X
H
H
L
Mode
Standby
Output Deselect
Read
Write
Output
High Z
High Z
DOUT
DIN
Power
ICC2, ICC3
ICC1
ICC1
ICC1
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Input Capacitance
(Except DQ Pins)
Capacitance (DQ Pins)
Input (E)
Input (W) Line
Sym
CI
CD/Q
CC
CW
Max
15
20
10
15
Unit
pF
pF
pF
pF
These parameters are sampled, not 100% tested.
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
2
Sept. 2001 Rev. 9
ECO #14605
EDI8F8257C
AC CHARACTERISTICS READ CYCLE
Symbol
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Disable to Output in High Z(1)
Output Enable to Output in Low Z (1)
Note: Parameter guaranteed, but not tested
70ns
Min
70
70
70
5
30
3
40
30
0
0
3
5
Max
85
85ns
Min
Max
85
85
5
35
3
45
35
0
100ns
Min
100
100
100
40
50
40
Max Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
JEDEC
TAVAV
TAVQV
TELQV
TELQX
TAVQX
TGLQV
TGLQX
Alt.
TRC
TAA
TACS
TCLZ
TOH
TOE
TOLZ
TEHQZ TCHZ
TGHQZ TOHZ
READ CYCLE 1 - W HIGH, G, E LOW
t
AVAV
A
ADDRESS 1
ADDRESS 2
t
AVQV
Q
t
AVQX
DATA 1
DATA 2
READ CYCLE 2 - W HIGH
t
AVAV
A
t
AVQV
E
t
ELQV
t
ELQX
G
t
EHQZ
t
GLQV
t
GLQX
Q
t
GHQZ
Sept. 2001 Rev. 9
ECO #14605
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI8F8257C
AC CHARACTERISTICS WRITE CYCLE
Symbol
JEDEC Alt.
TAVAV
TELWH
TELEH
TAVWL
TAVEL
TAVWH
TAVEH
TWLWH
TWLEH
TWHAX
TEHAX
TWHDX
TEHDX
TDVWH
TDVEH
TWC
TCW
TCW
TAS
TAS
TAW
TAW
TWP
TWP
TWR
TWR
TDH
TDH
TDW
TDW
70ns
Min Max
70
65
65
0
0
65
65
65
65
0
0
0
0
0
30
30
5
30
85ns
Min Max
85
70
70
0
0
70
70
70
70
0
0
0
0
0
35
35
5
35
100ns
Min
Max Units
100
80
80
0
0
80
80
80
80
0
0
0
0
0
40
40
5
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
Note 1: Parameter guaranteed, but not tested.
TWLQZ TWHZ
TWHQX TWLZ
WRITE CYCLE 1 - W CONTROLLED
t
AVAV
A
t
AVWH
t
ELWH
E
t
WHAX
t
AVWL
W
t
WLWH
t
DVWH
t
WHDX
D
DATA VALID
t
WLQZ
Q
HIGH Z
t
WHQX
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
4
Sept. 2001 Rev. 9
ECO #14605
EDI8F8257C
WRITE CYCLE 2 - E CONTROLLED
TAVAV
A
TAVEL
E
TAVEH
TWLEH
W
TDVEH
D
Q
HIGH Z
TEHDX
DATA VALID
TELEH
TEHAX
DATA RETENTION CHARACTERISTICS
Characteristic
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time
Operation Recovery TIme
*Read Cycle Time
LP VERSION ONLY
Typ
--
10
20
--
--
Max
70°C
85°C
--
--
125
200
--
--
185
250
--
--
Unit
V
µA
µA
ns
ns
Sym
VDD
ICCDR
TCDR
TR
Test Conditions
VDD = 0.2V
E
³
VDD -0.2V
VIN
³
VDD -0.2V
or VIN
£
0.2V
VDD
Min
2
2V
3V
--
--
0
TAVAV*
DATA RETENTION E CONTROLLED
DATA RETENTION MODE
VCC
TCDR
4.5V
VDD
4.5V
TR
E
E VDD-0.2V
Sept. 2001 Rev. 9
ECO #14605
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
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