STB10N60M2, STD10N60M2,
STP10N60M2, STU10N60M2
N-channel 600 V, 0.55 Ω typ., 7.5 A MDmesh™ M2 Power
MOSFETs in D²PAK, DPAK, TO-220 and IPAK packages
Datasheet - production data
Features
Order code
STB10N60M2
STD10N60M2
STP10N60M2
STU10N60M2
650 V
0.60 Ω
7.5 A
V
DS
@T
Jmax.
R
DS(on)
max.
I
D
Figure 1: Internal schematic diagram
Extremely low gate charge
Excellent output capacitance (C
OSS
) profile
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
These devices are N-channel Power MOSFETs
developed using MDmesh™ M2 technology.
Thanks to their strip layout and improved vertical
structure, these devices exhibit low on-resistance
and optimized switching characteristics,
rendering them suitable for the most demanding
high efficiency converters.
Table 1: Device summary
Order code
STB10N60M2
STD10N60M2
STP10N60M2
STU10N60M2
10N60M2
Marking
Package
D
2
PAK
DPAK
TO-220
IPAK
Packing
Tape and reel
Tube
March 2017
DocID024710 Rev 3
1/29
www.st.com
This is information on a product in full production.
Contents
STB10N60M2, STD10N60M2, STP10N60M2,
STU10N60M2
Contents
1
2
3
4
Electrical ratings ............................................................................. 3
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
Test circuits ..................................................................................... 9
Package information ..................................................................... 10
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
D²PAK (TO-263) type A package information ................................. 10
DPAK (TO-252) type A package information................................... 13
DPAK (TO-252) type C package information .................................. 15
DPAK (TO-252) type E package information................................... 17
TO-220 type A package information ................................................ 19
IPAK (TO-251) type A package information .................................... 21
IPAK (TO-251) type C package information .................................... 23
D²PAK and DPAK packing information ........................................... 25
5
Revision history ............................................................................ 28
2/29
DocID024710 Rev 3
STB10N60M2, STD10N60M2, STP10N60M2,
STU10N60M2
Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
V
GS
I
D
I
DM
(1)
P
TOT
dv/dt
(2)
dv/dt
(3)
T
stg
T
j
Notes:
(1)
Pulse
(2)
(3)
Parameter
Gate-source voltage
Drain current (continuous) at T
case
= 25 °C
Drain current (continuous) at T
case
= 100 °C
Drain current (pulsed)
Total dissipation at T
case
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
Value
±25
7.5
4.9
30
85
15
50
-55 to 150
Unit
V
A
A
W
V/ns
°C
limited by safe operating area.
I
SD
≤ 7.5 A, di/dt ≤ 400 A/μs; V
DS
peak < V
(BR)DSS
, V
DD
= 400 V
V
DS
≤ 480 V.
Table 3: Thermal data
Value
Symbol
R
thj-case
R
thj-pcb
R
thj-amb
Notes:
(1)
When
Parameter
Thermal resistance junction-case
Thermal resistance junction-pcb
(1)
Thermal resistance junction-
ambient
D
2
PAK
DPAK
TO-220
IPAK
Unit
1.47
30
50
62.5
100
°C/W
mounted on 1 inch² FR-4, 2 Oz copper board.
Table 4: Avalanche characteristics
Symbol
I
AR
(1)
E
AS
(2)
Notes:
(1)
(2)
Parameter
Avalanche current, repetitive or not repetitive
Single pulse avalanche energy
Value
1.5
110
Unit
A
mJ
Pulse width limited by T
jmax
.
Starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V.
DocID024710 Rev 3
3/29
Electrical characteristics
STB10N60M2, STD10N60M2, STP10N60M2,
STU10N60M2
2
Electrical characteristics
(T
case
= 25 °C unless otherwise specified)
Table 5: Static
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown
voltage
Zero gate voltage drain
current
Gate-body leakage
current
Gate threshold voltage
Static drain-source on-
resistance
Test conditions
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 600 V
V
GS
= 0 V, V
DS
= 600 V,
T
case
= 125 °C
(1)
V
DS
= 0 V, V
GS
= ±25 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 3 A
2
3
0.55
Min.
600
1
100
±10
4
0.60
µA
Typ.
Max.
Unit
V
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Notes:
(1)
Defined
µA
V
Ω
by design, not subject to production test.
Table 6: Dynamic
Symbol
C
iss
C
oss
C
rss
C
oss
eq.
(1)
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent output
capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
Min.
-
Typ.
400
22
0.84
83
6.4
13.5
2.1
7.2
Max.
-
-
-
-
-
-
-
-
Unit
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
-
-
pF
V
DS
= 0 to 480 V, V
GS
= 0 V
f = 1 MHz, I
D
= 0 A
V
DD
= 480 V, I
D
= 7.5 A,
V
GS
= 0 to 10 V (see
Figure 17:
"Test circuit for gate charge
behavior")
-
-
-
-
-
pF
Ω
R
G
Q
g
Q
gs
Q
gd
Notes:
(1)
nC
C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
.
Table 7: Switching times
Symbol
t
d(on)
t
r
t
d(off)
t
f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
V
DD
= 300 V, I
D
= 3.75 A
R
G
= 4.7 Ω, V
GS
= 10 V (see
Figure 16: "Test circuit for
resistive load switching times"
and
Figure 21: "Switching time
waveform")
Min.
-
-
-
-
Typ.
8.8
8
32.5
13.2
Max.
-
-
-
-
ns
Unit
4/29
DocID024710 Rev 3
STB10N60M2, STD10N60M2, STP10N60M2,
STU10N60M2
Table 8: Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Notes:
(1)
(2)
Electrical characteristics
Parameter
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
Min.
-
-
Typ.
Max.
7.5
30
1.6
Unit
A
A
V
ns
µC
A
ns
µC
A
V
GS
= 0 V, I
SD
= 7.5 A
I
SD
= 7.5 A, di/dt = 100 A/µs,
V
DD
= 60 V (see
Figure 18:
"Test circuit for inductive load
switching and diode recovery
times")
I
SD
= 7.5 A, di/dt = 100 A/µs,
V
DD
= 60 V, T
j
= 150 °C (see
Figure 18: "Test circuit for
inductive load switching and
diode recovery times")
-
-
-
-
-
-
-
270
2
14.4
376
2.8
15
Pulse width is limited by safe operating area.
Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
DocID024710 Rev 3
5/29
京公网安备 11010802033920号
EEWORLD
