Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
X5R Dielectric, 4 – 50 VDC (Commercial Grade)
Packaging C-Spec Ordering Options Table
Packaging Type
1
Bulk Bag/Unmarked
7" Reel/Unmarked
13" Reel/Unmarked
7" Reel/Marked
13" Reel/Marked
7" Reel/Unmarked/2mm pitch
2
13" Reel/Unmarked/2mm pitch
2
1
1
Packaging/Grade
Ordering Code (C-Spec)
Not required (Blank)
TU
7411 (EIA 0603 and smaller case sizes)
7210 (EIA 0805 and larger case sizes)
TM
7040 (EIA 0603 and smaller case sizes)
7215 (EIA 0805 and larger case sizes)
7081
7082
Default packaging is "Bulk Bag". An ordering code C-Spec is not required for "Bulk Bag" packaging.
The terms "Marked" and "Unmarked" pertain to laser marking option of capacitors. All packaging options labeled as "Unmarked" will contain capacitors
that have not been laser marked. Please contact KEMET if you require a laser marked option. For more information see "Capacitor Marking".
2
The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case
size devices. For more information regarding 2 mm pitch option see "Tape & Reel Packaging Information".
Dimensions – Millimeters (Inches)
W
L
T
B
S
EIA Size
Code
0201
0402
1
0603
0805
1206
2
1210
1
2
3
Metric Size
Code
0603
1005
1608
2012
3216
3225
L
Length
0.60 (0.024)
±0.03 (0.001)
1.00 (0.040)
±0.05 (0.002)
1.60 (0.063)
±0.15 (0.006)
2.00 (0.079)
±0.20 (0.008)
3.20 (0.126)
±0.20 (0.008)
3.20 (0.126)
±0.20 (0.008)
W
Width
0.30 (0.012)
±0.03 (0.001)
0.50 (0.020)
±0.05 (0.002)
0.80 (0.032)
±0.15 (0.006)
1.25 (0.049)
±0.20 (0.008)
1.60 (0.063)
±0.20 (0.008)
2.50 (0.098)
±0.20 (0.008)
T
Thickness
B
Bandwidth
0.15 (0.006)
±0.05 (0.002)
0.30 (0.012)
±0.10 (0.004)
0.35 (0.014)
±0.15 (0.006)
0.50 (0.02)
±0.25 (0.010)
0.50 (0.02)
±0.25 (0.010)
0.50 (0.02)
±0.25 (0.010)
S
Separation
Minimum
N/A
0.30 (0.012)
0.70 (0.028)
0.75 (0.030)
N/A
Mounting
Technique
Solder Reflow
Only
See Table 2 for
Thickness
Solder Wave or
Solder Reflow
Solder Reflow
Only
For capacitance values ≥ 4.7 µF add 0.15 (0.006) to the width and length tolerance dimensions.
For capacitance values ≥ 22 µF add 0.10 (0.004) to the positive bandwidth tolerance dimension.
3
For capacitance values ≥ 22 µF add 0.10 (0.004) to the length and width tolerance dimension and add 0.15 (0.006) to the positive bandwidth tolerance
I bought the micro2440sdk development board from Friendly Arm around July last year. I am now transferring it to you. I am willing to answer questions about bootloader and wince driver. I will also gi...
I seem to have found a solution in the previous post, but unfortunately, this problem occurred again, and the previous method did not work. This time, after clicking Query, the Programmer will crash a...
When I was reading the program, I suddenly found that volatile GPIO PA @ 0x5000; volatile GPIO PB @ 0x5005; What does the @ symbol mean? I would like to ask you experts! It would be better if you can ...
[i=s]This post was last edited by le062 on 2018-5-20 21:17[/i] Target chip: Jingwei Qili HME-M7 Basic information of the chip: [list=1] [*]FPGA logic resources: 12K LUT4 speed 200M [*]Cortex-M3, speed...
[i=s] This post was last edited by xxTLC on 2014-1-3 15:49 [/i] Launchpad, 200MHz, 60s, DMA memory access speed test. Key code: void SysCtlOC(){ uint32_t ui32RCC, ui32RCC2; ui32RCC = HWREG(0x400FE060)...
The two programs each have static variables or static areas. What is the difference between their static areas and the static areas of the operating system (where events and mutexes are stored)?...
Embedded System
京公网安备 11010802033920号
EEWORLD
