GS88237BB/D-xxxV
119- & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
256K x 36
9Mb SCD/DCD Sync Burst SRAM
250 MHz–200 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Functional Description
Applications
The GS88237BB/D-xxxV is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
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Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
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Parameter Synopsis
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x36)
-250
2.5
4.0
330
-200
2.5
5.0
270
Unit
ns
ns
mA
Rev: 1.06 12/2008
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Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS88237BB/D-xxxV operates on a 1.8 V or 2.5 V power
supply. All inputs are 1.8 V or 2.5 V compatible. Separate output
power (V
DDQ
) pins are used to decouple output noise from the
internal circuits and are 1.8 V or 2.5 V compatible.
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• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-bump and 165-bump BGA packages
• RoHS-compliant 119-bump and 165-bump BGA packages
available
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
SCD and DCD Pipelined Reads
The GS88237BB/D-xxxV is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
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es
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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© 2003, GSI Technology
GS88237BB/D-xxxV
GS88237BB/D-xxxV BGA Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
B
A
, B
B
, B
C
, B
D
NC
NC
CK
BW
GW
E
1
E
3
E
2
G
ADV
ADSC, ADSP
ZZ
FT
LBO
PE
ZQ
TMS
TDI
TDO
TCK
MCL
V
DD
V
SS
V
DDQ
SCD
Type
I
I
I/O
I
—
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
No Connect
No Connect
Byte Write—Writes all enabled bytes; active low
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Burst address counter advance enable; active l0w
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Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
Linear Burst Order mode; active low
9th Bit Enable; active low (119-bump BGA only)
Flow Through or Pipeline mode; active low
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FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect Low
Single Cycle Deselect/Dual Cyle Deselect Mode Control
Core power supply
I/O and Core Ground
Output driver power supply
N
Rev: 1.06 12/2008
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I
O
I
—
—
I
I
I
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Output Enable; active low
N
Chip Enable; active low
ew
D
Clock Input Signal; active high
es
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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MCU
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