W78ERD2 Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
PIN CONFIGURATIONS............................................................................................................. 4
PIN DESCRIPTION..................................................................................................................... 5
BLOCK DIAGRAM ...................................................................................................................... 6
FUNCTIONAL DESCRIPTION.................................................................................................... 7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7.
8.
9.
10.
RAM ................................................................................................................................... 7
Timers 0, 1 and 2............................................................................................................... 7
Clock .................................................................................................................................. 8
Crystal Oscillator................................................................................................................ 8
External Clock.................................................................................................................... 8
Power Management........................................................................................................... 8
Reduce EMI Emission ....................................................................................................... 8
Reset.................................................................................................................................. 8
SPECIAL FUNCTION REGISTER .............................................................................................. 9
PORT 4 AND BASE ADDRESS REGISTERS.......................................................................... 33
INTERRUPT.............................................................................................................................. 35
ENHANCED FULL DUPLEX SERIAL PORT............................................................................ 36
10.1
10.2
10.3
10.4
10.5
10.6
MODE 0 ....................................................................................................................... 36
MODE 1 ....................................................................................................................... 37
MODE 2 ....................................................................................................................... 38
MODE 3 ....................................................................................................................... 39
Framing Error Detection............................................................................................... 41
Multiprocessor Communications.................................................................................. 41
PCA Capture Mode ...................................................................................................... 46
16-bit Software Timer Comparator Mode .................................................................... 46
High Speed Output Mode ............................................................................................ 47
Pulse Width Modulator Mode....................................................................................... 47
Watchdog Timer........................................................................................................... 48
11.
PROGRAMMABLE COUNTER ARRAY (PCA) ........................................................................ 43
11.1
11.2
11.3
11.4
11.5
-1-
Publication Release Date: April 20, 2005
Revision A4
W78ERD2
12.
13.
14.
15.
16.
17.
HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT) ................... 48
12.1
Using the WDT............................................................................................................. 48
DUAL DPTR .............................................................................................................................. 49
IN-SYSTEM PROGRAMMING (ISP) MODE ............................................................................ 49
H/W REBOOT MODE (BOOT FROM LDROM)........................................................................ 51
OPTION BITS ........................................................................................................................... 56
ELECTRICAL CHARACTERISTICS ......................................................................................... 57
17.1
17.2
17.3
18.
19.
Absolute Maximum Ratings ......................................................................................... 57
D.C. Characteristics ..................................................................................................... 57
A.C. Characteristics ..................................................................................................... 59
TIMING WAVEFORMS ............................................................................................................. 61
TYPICAL APPLICATION CIRCUITS ........................................................................................ 63
19.1
19.2
External Program Memory and Crystal........................................................................ 63
Expanded External Data Memory and Oscillator......................................................... 64
20.
21.
PACKAGE DIMENSIONS ......................................................................................................... 65
APPLICATION NOTE ............................................................................................................... 67
21.1
21.2
In-system Programming Software Examples............................................................... 67
How to Use Programmable Counter Array .................................................................. 71
22.
VERSION HISTORY ................................................................................................................. 72
-2-
W78ERD2
1. GENERAL DESCRIPTION
The W78ERD2 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78ERD2 is fully compatible with the standard 8052. The
W78ERD2 contains a 64K bytes of main Flash EPROM and a 4K bytes of auxiliary Flash EPROM
which allows the contents of the 64KB main Flash EPROM to be updated by the loader program
located at the 4KB auxiliary Flash EPROM ROM; 256 bytes of on-chip RAM, 1K AUX-RAM; four 8-bit
bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a
serial port. These peripherals are supported by a nine sources four level interrupt capability. To
facilitate programming and verification, the Flash EPROM inside the W78ERD2 allows the program
memory to be programmed and read electronically. Once the code is confirmed, the user can protect
the code for security.
The W78ERD2 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit CMOS microcontroller
Pin compatible with standard 80C52
Instruction-set compatible with MCS-51
Four 8-bit I/O Ports
One extra 4-bit I/O port, interrupt, chip select function
Three 16-bit Timers
Programmable clock out
Programmable Counter Array (PCA): PWM, Capture, Compare, Watchdog
9
interrupt sources with 4 levels of priority
One enhanced full duplex serial port with framing error detection and automatic address
recognition
64KB In-system Programmable Flash EPROM (AP Flash EPRAOM)
4KB Auxiliary Flash EPROM for loader program (LD Flash EPROM)
256+1K bytes of on-chip RAM. (Including 1K bytes of AUX-RAM, software selectable)
Software Reset
12 clocks per machine cycle operation (default). Speed up to 40 MHz.
6
clocks per machine cycle operation which is set by the writer. Speed up to 20 MHz.
2 DPTR registers
Low EMI (inhibit ALE)
Built-in power management with idle mode and power down mode
Code protection
Packages:
−
DIP 40: W78ERD2A40DN
−
PLCC 44: W78ERD2A40PN
−
QFP 44: W78ERD2A40FN
Publication Release Date: April 20, 2005
Revision A4
-3-
W78ERD2
3. PIN CONFIGURATIONS
40-Pin DIP
T2, P1.0
T2EX, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
44-Pin PLCC
T
2
E
X
,
P
1
.
1
/
I
N
T
3
,
P
4 V
. D
2 D
44-Pin QFP
T
2
E
X
,
P P
1 1
. .
2 1
/
I
N
T
3
,
P
4 V
. D
2 D
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
P
1
.
4
P
1
.
3
P
1
.
2
T
2
,
P
1
.
0
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
P
1
.
4
P
1
.
3
T
2
,
P
1
.
0
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
6 5 4 3 2 1 44 43 42 41 40
7
39
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X
T
A
L
1
V
S
S
P
4
.
0
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
1
2
44 43 42 41 40 39 38 37 36 35 34
33
32
31
3
30
4
29
5
28
6
27
7
26
8
9
25
10
24
23
11
12 13 14 15 16 17 18 19 20 21 22
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X V
T S
A S
L
1
P
4
.
0
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
-4-
W78ERD2
4. PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTIONS
EA
I
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
the
EA
pin is high.
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no
PSEN
strobe signal outputs originate from this pin.
PSEN
O H
ALE
O H
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: ground potential.
POWER SUPPLY: Supply voltage for operation.
RST
XTAL1
XTAL2
V
SS
V
DD
P0.0
−
P0.7
P1.0
−
P1.7
P2.0
−
P2.7
P3.0
−
P3.7
P4.0
−
P4.3
I L
I
O
I
I
I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
I/O H PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H PORT 4: A bi-directional I/O. See details below.
* Note: TYPE
I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1.
Example:
P4
MOV
MOV
ORL
ANL
REG
A, P4
P4, #00000001B
P4, #11111110B
0D8H
; Output data "A" through P4.0
−
P4.3.
; Read P4 status to Accumulator.
P4, #0AH
-5-
Publication Release Date: April 20, 2005
Revision A4
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