®
EMIF01-10005W5
EMI FILTER
INCLUDING ESD PROTECTION
Application Specific Discretes
A.S.D.
TM
MAIN APPLICATIONS
Where EMI filtering in ESD sensitive equipment is required :
Computers and printers
Communication systems
Mobile phones
MCU Boards
DESCRIPTION
The EMIF01-10005W5 is a highly integrated array
designed to suppress EMI / RFI noise in all systems
subjected to electromagnetic interferences.
Additionally, this filter includes an ESD protection circuitry
which prevents the protected device from destruction when
subjected to ESD surges up to 15 kV.
SOT323-5L
FUNCTIONAL DIAGRAM
BENEFITS
Cost-effectiveness compared to discrete solution
EMI bi-directional low-pass filter
High efficiency in ESD suppression.
High flexibility in the design of high density boards
Very low PCB space consuming : 4.2 mm
2
typically
High reliability offered by monolithic integration
I1
GND
I2
R
I/O
= 100
Ω
C
IN
= 50pF
Filtering response
dB
0
O1
O2
COMPLIES WITH THE FOLLOWING STANDARD:
IEC 1000-4-2
15kV
8 kV
(air discharge)
(contact discharge)
ESD response to IEC1000-4-2 (16 kV air discharge)
-10
-20
f(MHz)
-30
1
10
100
1000 2000
TM
: ASD is trademark of STMicroelectronics.
May 1999 - Ed: 1
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EMIF01-10005W5
ABSOLUTE MAXIMUM RATINGS
(T
amb
= 25 °C)
Symbol
V
PP
T
j
T
op
T
stg
T
L
Parameter and test conditions
ESD discharge IEC1000-4-2, air discharge
ESD discharge IEC1000-4-2, contact discharge
Junction temperature
Operating temperature range
Storage temperature range
Lead solder temperature (10 second duration)
Value
16
9
150
-40 to + 85
-55 to +150
260
Unit
kV
°C
°C
°C
°C
ELECTRICAL CHARACTERISTICS
(T
amb
= 25 °C)
Symbol
V
BR
I
RM
V
RM
V
CL
Rd
I
PP
R
I/O
C
IN
Parameter
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
Clamping voltage
Dynamic impedance
Peak pulse current
Series resistance between Input
and Output
Input capacitance per line
slope : 1 / R
d
I
PP
V
CL
V
BR
V
RM
I
RM
I
R
I
V
Symbol
V
BR
I
RM
R
I/O
R
d
C
IN
I
R
= 1 mA
V
RM
= 3V
Test conditions
Min.
6
Typ.
7
Max.
8
1
Unit
V
µA
Ω
Ω
pF
80
I
pp
= 10 A, t
p
= 2.5
µs
(see note 1)
at 0V bias
100
1
50
120
Note 1 : to calculate the ESD residual voltage, please refer to the paragraph "ESD PROTECTION" on pages 4 & 5
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EMIF01-10005W5
TECHNICAL INFORMATION
FREQUENCY BEHAVIOR
The EMIF01-10005W5 is firstly designed as an EMI/RFI filter. This low-pass filter is characterized by the following
parameters:
- Cut-off frequency
- Insertion loss
- High frequency rejection
Fig A1:
EMIF01-10005W5 frequency response curve.
dB
0
-10
-20
f(MHz)
-30
1
10
100
1000 2000
Figure A1 gives these parameters, in particular the signal rejection at the GSM frequency is about -24dB at 900MHz,
Fig A2:
Measurement conditions
TRACKING GENERATOR
SPECTRUM ANALYSER
SMA
TEST BOARD
EMIF01
50Ω
TG OUT
SMA
RF IN
Vg
50Ω
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EMIF01-10005W5
ESD PROTECTION
In addition to its filtering function, the EMIF01-10005W5 is particularly optimized to perform ESD protection.
ESD protection is based on the use of device which clamps at :
V
CL
= V
BR
+ R
d
.I
PP
This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the first stage S1 and
then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output
voltage very low at the Vout level.
Fig A3 :
ESD clamping behavior
Rg
R
ESD
Surge
Rd
Vg
Vin
Vbr
Rd
Vout
Vbr
Rload
S1
EMIF01-10005W5
S2
Device to be protected
To have a good approximation of the remaining voltages at both Vin and Vout stages, we provide the typical dynamical
resistance value Rd. By taking into account these following hypothesis : R>>Rd, R
G
>>Rd and Rload>>Rd, it gives these
formulas:
Vin
=
Rg.Vbr
+
Rd.Vg
Rg
Vout
=
R.Vbr
+
Rd.Vin
R
The results of the calculation done for V
G
=8kV, R
G
=330Ω (IEC1000-4-2 standard) and V
BR
=7V (typ.) give:
Vin = 31.2 V
Vout = 7.3 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this
approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at
the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R.
Fig A4 :
Measurement conditions
ESD
SURGE
16kV
Air
Discharge
TEST BOARD
EMIF01
Vin
Vout
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EMIF01-10005W5
The measurements shown here after illustrate very clearly (Fig. A5a) the high efficiency of the ESD protection :
- no influence of the parasitic inductances on Vout stage
- Vout clamping voltage very close to V
BR
Fig A5 :
Remaining voltage at both stages S1 (Vin) and S2 (Vout) during ESD surge
a) Positive surge
b) Negative surge
Please note that the EMIF01-10005W5 is not only acting
for positive ESD surges but also for negative ones. For
these kind of disturbances it clamps close to ground
voltage as shown in Fig. A5b.
NOTE: DYNAMIC RESISTANCE MEASUREMENT
As the value of the dynamic resistance remains stable for
a surge duration lower than 20µs, the 2.5µs rectangular
surge is well adapted. In addition both rise and fall times
are optimized to avoid any parasitic phenomenon during
the measurement of Rd.
Fig A6 :
Rd measurement current wave
I
I
PP
t
2 µs
2.5 µs
2.5µs duration measurement wave
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