DS1845E-010 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Analog mixed-signal IC> converter> DS1845E-010

DS1845E-010: DescriptionDUAL 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14; CategoryAnalog mixed-signal IC converter; File Size99KB，13 Pages; ManufacturerDALLAS; Websitehttp://www.dalsemi.com

Download Datasheet Parametric View All

DS1845E-010 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	DS1845E-010	-	-	View	Buy Now

DS1845E-010 Overview

DUAL 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14

DS1845E-010 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	DALLAS
package instruction	0.173 INCH, TSSOP-14
Reach Compliance Code	unknow
control interface	2-WIRE SERIAL
Converter type	DIGITAL POTENTIOMETER
JESD-30 code	R-PDSO-G14
Number of functions	1
Number of positions	256
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	3/5 V
Certification status	Not Qualified
resistance law	LINEAR
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Nominal total resistance	10000 Ω

Preview

Download Datasheet

View All

DS1845

Dual NV Potentiometer and Memory

www.dalsemi.com

FEATURES

Two linear taper potentiometers

−

DS1845-010 one 10k, 100 position &

one 10k, 256 position

−

DS1845-050 one 10k, 100 position &

one 50k, 256 postition

−

DS1845-100 one 10k, 100 position &

one 100k, 256 position

256 bytes of EEPROM memory

Access to data and potentiometer control via

a 2-wire interface

External Write Enable pin to protect data and

potentiometer settings

Nonvolatile wiper storage in 2 bytes of

address space

Operates from 3V or 5V supplies

Packaging: Flip Chip Package, 16-ball

STPBGA, 14-pin TSSOP

Industrial operating temperature: -40ºC to

+85ºC

Programming temperature: 0ºC to +70ºC

PIN ASSIGNMENT

SDA

SCL

GND

Vcc

14-Pin TSSOP (173 mil)

14-Pin Flip Chip (100 x 100 mils)

16-BALL STPBGA (4 x 4 mm)

See Mech. Drawing Section

PIN DESCRIPTION

GND

SDA

SCL

A0, A1, A2

H0, H1

L 0, L1

W0, W1

- 3V or 5V Power Supply Input

- Ground

- 2-wire Serial Data

Input/Output

- 2-wire Serial Clock Input

- Write Protect Input

- Address Inputs

- High-End of Potentiometer

- Low-End of Potentiometer

- Wiper Terminal of

Potentiometer

DESCRIPTION

The DS1845 Dual NV Potentiometer and Memory consists of one=100-position linear taper

potentiometer, one=256-position linear taper potentiometer, 256 bytes of EEPROM memory, and a 2-wire

interface. The device provides an ideal method for setting bias voltages and currents in control

applications using a minimum of circuitry. The EEPROM memory allows a user to store configuration

or calibration data for a specific system or device as well as provide control of the potentiometer wiper

settings. Any type of user information may reside in the first 248 bytes of this memory. The next two

addresses of EEPROM memory are for potentiometer settings and the remaining 6 bytes of memory are

reserved. These reserved and potentiometer registers should not be used for data storage. Access to this

EEPROM is via an industry standard 2-wire bus. The interface I/O pins consist of SDA and SCL. The

wiper position of the DS1845, as well as EEPROM data, can be hardware write-protected using the Write

Protect (WP) input pin.

1 of 13

051900

DS1845

H0, H1 –

These are the high-end terminals of the potentiometers. For both potentiometers, it is not

required that these terminals be connected to a potential greater than the low-end terminal of the

potentiometer. Voltage applied to the high end of the potentiometers cannot exceed the power supply

voltage, V

, or go below ground.

L0, L1 –

These are the low-end terminals of the potentiometers. It is not required that these terminals be

connected to a potential less than the high-end terminals of the pot. Voltage applied to the low end of the

potentiometers cannot exceed the power-supply voltage, V

, or go below ground.

W0, W1

- Wiper of the Potentiometer. This pin is the wiper terminal of the potentiometer. The bytes in

EEPROM memory locations F8h and F9h determine each wiper’s setting. Voltage applied to either

wiper terminal cannot exceed the power-supply voltage, V

, or go below ground.

MEMORY ORGANIZATION

The DS1845’s serial EEPROM is internally organized with 256 words of 1 byte each. Each word requires

an 8-bit address for random word addressing. The byte at address F9h determines the wiper setting for

potentiometer 0, which contains 100 positions. Writing values above 63h to this address sets the wiper to

its uppermost position. The byte at address F8h determines the wiper setting for potentiometer 1, which

contains 256 positions (00h to FFh). Address locations FAh though FFh are reserved and should not be

written.

DEVICE OPERATION

Clock and Data Transitions:

The SDA pin is normally pulled high with an external resistor or device.

Data on the SDA pin may only change during SCL low time periods. Data changes during SCL high

periods will indicate a start or stop conditions depending on the conditions discussed below. Refer to the

timing diagram Fig 2 for further details.

Start Condition:

A high-to-low transition of SDA with SCL high is a start condition which must

precede any other command. Refer to the timing diagram Fig 2 for further details.

Stop Condition:

A low-to-high transition of SDA with SCL high is a stop condition. After a read

sequence, the stop command places the DS1845 into a low-power mode. Refer to the timing diagram Fig

2 for further details.

Acknowledge:

All address and data byte are transmitted via a serial protocol. The DS1845 pulls the

SDA line low during the ninth clock pulse to acknowledge that it has received each word.

Standby Mode:

The DS1845 features a low-power mode that is automatically enabled after power-on,

after a stop command, and after the completion of all internal operations.

2-Wire Interface Reset:

After any interruption in protocol, power loss, or system reset, the following

steps reset the DS1845.

1. Clock up to nine cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition while SDA is high.

3 of 13

DS1845

Device Addressing:

The DS1845 must receive an 8-bit device address word following a start condition

to enable a specific device for a read or write operation. The address word is clocked into the DS1845

MSB to LSB. The address word consists of Ah (1010) followed by A2, A1, and A0 then the R/W

(READ/WRITE) bit. If the R/W bit is high, a read operation is initiated. The R/W is low, a write

operation is initiated. For a device to become active, the values of A2, A1 and A0 must be the same as

the hard-wired address pins on the DS1845. Upon a match of written and hard-wired addresses, the

DS1845 will output a zero for one clock cycle as an acknowledge. If the address does not match the

DS1845 returns to a low-power mode.

Write Operations:

After receiving a matching address byte with the R/W bit set low, the device goes

into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to the

device to define the address where the data is to be written. After the reception of this byte, the DS1845

will transmit a zero for one clock cycle to acknowledge the receipt of the address. The master must then

transmit an 8-bit data word to be written into this address. The DS1845 will again transmit a zero for one

clock cycle to acknowledge the receipt of the data. At this point the master must terminate the write

operation with a stop condition. The DS1845 then enters an internally timed write process T

to the

EEPROM memory. All inputs are disabled during this byte write cycle.

The DS1845 is capable of an 8-byte page write. A page write is initiated the same way as a byte write,

but the master does not send a stop condition after the 1

byte. Instead, after the slave acknowledges

receipt of the data byte, the master can send up to seven more bytes using the same nine-clock sequence.

The master must terminate the write cycle with a stop condition or the data clocked into the DS1845 will

not be latched into permanent memory.

Acknowledge Polling:

Once the internally-timed write has started and the DS1845 inputs are disabled,

acknowledge polling can be initiated. The process involves transmitting a start condition followed by the

device address. The R/W bit signifies the type of operation that is desired. The read or write sequence

will only be allowed to proceed if the internal write cycle has completed and the DS1845 responds with a

zero.

Read Operations:

After receiving a matching address byte with the R/W bit set high, the device goes

into the read mode of operation. There are three read operations: current address read, random read and

sequential address read.

CURRENT ADDRESS READ

The DS1845 has an internal address register that maintains the address used during the last read or write

operation, incremented by one. This data is maintained as long as V

is valid. If the most recent

address was the last byte in memory, then the register resets to the first address. This address stays valid

between operations as long as power is available.

Once the device address is clocked in and acknowledged by the DS1845 with the R/W bit set to high, the

current address data word is clocked out. The master does not respond with a zero, but does generate a

stop condition afterwards.

4 of 13

DS1845

RANDOM READ

A random read requires a dummy byte write sequence to load in the data word address. Once the device

and data address bytes are clocked in by the master, and acknowledged by the DS1845, the master must

generate another start condition. The master now initiates a current address read by sending the device

address with the read/write bit set high. The DS1845 will acknowledge the device address and serially

clocks out the data byte.

SEQUENTIAL ADDRESS READ

Sequential reads are initiated by either a current address read or a random address read. After the master

receives the first data byte, the master responds with an acknowledge. As long as the DS1845 receives

this acknowledge after a byte is read, the master may clock out additional data words from the DS1845.

After reaching address FFh, it resets to address 00h.

The sequential read operation is terminated when the master initiates a stop condition. The master does

not respond with a zero.

For a more detailed description of 2-wire theory of operation, refer to the following section.

2-WIRE SERIAL PORT OPERATION

The 2-wire serial port interface supports a bi-directional data transmission protocol with device

addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as

a receiver. The device that controls the message is called a “master.” The devices that are controlled by

the master are “slaves.” The bus must be controlled by a master device that generates the serial clock

(SCL), controls the bus access, and generates the START and STOP conditions. The DS1845 operates as

a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.

The following I/O terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2. Timing diagrams for

the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is

provided in the AC Electrical Characteristics table for 2-wire serial communications.

The following bus protocol has been defined:

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in

the data line while the clock line is HIGH will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy:

Both data and clock lines remain HIGH.

Start data transfer:

A change in the state of the data line from HIGH to LOW while the clock is HIGH

defines a START condition.

Stop data transfer:

A change in the state of the data line from LOW to HIGH while the clock line is

HIGH defines the STOP condition.

5 of 13

Recommended Resources

Infrared anti-theft alarm circuit 2

Thyristor AC voltage regulating circuit for projector lamp

Interference-free electric fan speed regulator circuit

Infrared multi-channel programming remote control

[Xiao Meige SOPC Learning Notes] Set Eclipse to automatically save source code files before compiling (build): [align=center][b][size=5] [/size][/b][/align] [align=center][b][size=5]Set Eclipse to automatically save source code files before compiling (build) [/size][/b][/align] [align=center][b][size=5] [/size...; 芯航线跑堂 FPGA/CPLD

[TI DLP Creative Collection] + Energy switch and password security anti-theft: DLP technology is used to transmit energy, and the energy is exchanged in the form of photoelectric conversion or light to light. At the same time, it can include spectra of different frequencies whil...; hellokt43 TI Technology Forum

Does anyone know how to display four channels of video evenly on DM642?: Please help me answer this question....; 一生有你123 DSP and ARM Processors

Notes on using operational amplifiers: Detailed explanation of the precautions for using operational amplifiers...; loveroast Analog electronics

How to multithread?: My version is v1.9.3, there is no _thread module...; sgz10010010 MicroPython Open Source section

Let's talk about PC installation configuration suitable for electronic engineers: Computer hardware technology is developing very fast. It can be said that it changes every year and changes a lot in three years. Although, for electronic engineers, PC hardware should also belong to ...; chunyang Talking

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components