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MAX9322ECY

Description
LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver
Categorylogic    logic   
File Size175KB,13 Pages
ManufacturerMaxim
Websitehttps://www.maximintegrated.com/en.html
Download Datasheet Parametric Compare View All

MAX9322ECY Overview

LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver

MAX9322ECY Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMaxim
Parts packaging codeQFP
package instruction10 X 10 MM, 1 MM HEIGHT, MS-206, TQFP-52
Contacts52
Reach Compliance Code_compli
Other featuresLVECL MODE OPERATING RANGE IS -2.375V TO -3.8V
series9322
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-PQFP-G52
JESD-609 codee0
length10 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level3
Number of functions1
Number of inverted outputs
Number of terminals52
Actual output times15
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTQFP
Encapsulate equivalent codeTQFP52,.47SQ,25
Package shapeSQUARE
Package formFLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)245
power supply+-2.375/+-3.8 V
Prop。Delay @ Nom-Su1.25 ns
propagation delay (tpd)1.175 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.056 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.8 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyBIPOLAR
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width10 mm
minfmax93 MHz
19-2544; Rev 1; 12/02
LVECL/LVPECL 1:15 Differential
Divide-by-1/Divide-by-2 Clock Driver
General Description
The MAX9322 low-skew 1:15 differential clock driver
reproduces or divides one of two differential input clocks
at 15 differential outputs. An input multiplexer selects from
one of two input clocks with input switching frequency in
excess of 1.0GHz. The 15 outputs are arranged in four
banks with 2, 3, 4, and 6 outputs, respectively. Each
output bank is individually programmable to provide a
divide-by-1 or divide-by-2 frequency function.
The MAX9322 operates in LVPECL systems with a
+2.375V to +3.8V supply or in LVECL systems with a
-2.375V to -3.8V supply. A V
BB
reference output pro-
vides compatibility with single-ended clock input sig-
nals and a master reset input provides a simultaneous
reset on all outputs.
The MAX9322 is available in 52-pin TQFP and 68-pin
QFN packages and is specified for operation over
-40°C to +85°C. For 1:10 clock drivers, refer to the
MAX9311/MAX9313 data sheet. For 1:5 clock drivers,
refer to the MAX9316 data sheet.
o
300mV Differential Output at 1.0GHz
o
900ps Propagation Delay
o
Selectable Divide-by-1 or Divide-by-2 Frequency
Outputs
o
Multiplexed 2:1 Input Function
o
LVECL Operation from V
EE
= -2.375V to -3.8V
o
LVPECL Operation from V
CC
= +2.375V to +3.8V
o
ESD Protection: > 2kV Human Body Model
Features
o
1.2ps (RMS) Maximum Random Jitter
MAX9322
Ordering Information
PART
MAX9322ECY
MAX9322ETK*
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
52 TQFP
68 QFN
Applications
Precision Clock Distribution
Low-Jitter Data Repeaters
Central-Office Backplane Clock Distribution
DSLAM Backplane
Base Stations
ATE
*Future
product—contact factory for availability.
Pin Configurations
TOP VIEW
VCCO
VCCO
VCCO
40
39
VCCO
2
38
QC0
3
37
QC0
4
36
QC1
5
35
QC1
6
7
8
32
QC3
9
31
QC3
30
VCCO
29
N.C.
34
QC2
33
QC2
28
N.C.
27
VCCO
26
QA0
QA0
QA1
QA1
QB0
QB0
QB1
QB1
QB2
42
24
52
51
50
49
48
47
46
45
44
43
41
V
CC
MR
FSELA
1
Typical Operating Circuit
FSELB
CLK0
CLK0
CLK_SEL
CLK1
MAX9322
MAX9322
Z
O
= 50Ω
Q_
RECEIVER
CLK1
V
BB
10
FSELC
11
FSELD
12
Z
O
= 50Ω
Q_
V
EE
13
14
15
16
17
18
19
20
21
22
23
QD5
QD5
QD4
QD4
QD3
QD3
QD2
QD2
QD1
QD1
QD0
QB2
25
50Ω
50Ω
VCCO
TQFP
V
TT
= V
CC
- 2.0V
Pin Configurations continued at end of data sheet.
________________________________________________________________
Maxim Integrated Products
QD0
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

MAX9322ECY Related Products

MAX9322ECY MAX9322 MAX9322ETK
Description LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver
Is it Rohs certified? incompatible - incompatible
Maker Maxim - Maxim
Parts packaging code QFP - QFN
package instruction 10 X 10 MM, 1 MM HEIGHT, MS-206, TQFP-52 - QFN-68
Contacts 52 - 68
Reach Compliance Code _compli - _compli
Other features LVECL MODE OPERATING RANGE IS -2.375V TO -3.8V - LVECL MODE OPERATING RANGE IS -2.375V TO -3.8V
series 9322 - 9322
Input adjustment DIFFERENTIAL MUX - DIFFERENTIAL MUX
JESD-30 code S-PQFP-G52 - S-XQCC-N68
JESD-609 code e0 - e0
length 10 mm - 10 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER - LOW SKEW CLOCK DRIVER
Number of functions 1 - 1
Number of terminals 52 - 68
Actual output times 15 - 15
Maximum operating temperature 85 °C - 85 °C
Minimum operating temperature -40 °C - -40 °C
Package body material PLASTIC/EPOXY - UNSPECIFIED
encapsulated code TQFP - VQCCN
Encapsulate equivalent code TQFP52,.47SQ,25 - LCC68,.4SQ,20
Package shape SQUARE - SQUARE
Package form FLATPACK, THIN PROFILE - CHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 245 - NOT SPECIFIED
power supply +-2.375/+-3.8 V - +-2.375/+-3.8 V
Prop。Delay @ Nom-Su 1.25 ns - 1.25 ns
propagation delay (tpd) 1.175 ns - 1.175 ns
Certification status Not Qualified - Not Qualified
Same Edge Skew-Max(tskwd) 0.056 ns - 0.056 ns
Maximum seat height 1.2 mm - 0.9 mm
Maximum supply voltage (Vsup) 3.8 V - 3.8 V
Minimum supply voltage (Vsup) 2.375 V - 2.375 V
Nominal supply voltage (Vsup) 3.3 V - 3.3 V
surface mount YES - YES
technology BIPOLAR - BIPOLAR
Temperature level INDUSTRIAL - INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb)
Terminal form GULL WING - NO LEAD
Terminal pitch 0.65 mm - 0.5 mm
Terminal location QUAD - QUAD
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED
width 10 mm - 10 mm
minfmax 93 MHz - 93 MHz

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