Features
•
Fast Read Access Time – 120 ns
•
Automatic Page Write Operation
•
•
•
•
•
•
•
•
•
•
– Internal Address and Data Latches for 128 Bytes
– Internal Control Timer
Fast Write Cycle Time
– Page Write Cycle Time – 10 ms Maximum
– 1 to 128-byte Page Write Operation
Low Power Dissipation
– 80 mA Active Current
– 300 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 10
4
or 10
5
Cycles
– Data Retention: 10 Years
Operating Range: 4.5V to 5.5V, -55 to +125°C
CMOS and TTL Compatible Inputs and Outputs
Batch Tested for 10 Krad TID and 70 MeV Latch-up Capability
JEDEC Approved byte-Wide Pinout
435 Mils Wide 32-Pin Flat Pack Package
AT28C010-12DK Mil
Space
1-megabit
(128K x 8)
Paged Parallel
EEPROMs
AT28C010-12DK
Description
The AT28C010-12DK is a high-performance Electrically Erasable and Programmable
Read-Only Memory. Its one megabit of memory is organized as 131,072 words by 8
bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 120 ns with power dissipation of just 440 mW. When the device
is deselected, the CMOS standby current is less than 300
µA.
The AT28C010-12DK is accessed like a Static RAM for the read or write cycle without
the need for external components. The device contains a 128-byte page register to
allow writing of up to 128 bytes simultaneously. During a write cycle, the address and
1 to 128 bytes of data are internally latched, freeing the address and data bus for
other operations. Following the initiation of a write cycle, the device will automatically
write the latched data using an internal control timer. The end of a write cycle can be
detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected
a new access for a read or write can begin.
Atmel's 28C010 has additional features to ensure high quality in manufacturing. The
device utilizes internal error correction for extended endurance and improved data
retention characteristics. An optional software data protection mechanism is available
to guard against inadvertent writes. The device also includes an extra 128 bytes of
EEPROM for device identification or tracking.
Preliminary
Rev. 4259A–AERO–06/03
1
Pin Configuration
Pin Name
A0 - A16
CE
OE
WE
I/O0 - I/O7
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
FLATPACK
Top View
A16
A15
A12
A7
A6
NC
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
NC
WE
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Block Diagram
2
AT28C010-12DK
4259A–AERO–06/03
AT28C010-12DK
Device Operation
•
READ:
The AT28C010-12DK is accessed like a Static RAM. When CE and OE are
low and WE is high, the data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are put in the high impedance
state when either CE or OE is high. This dual-line control gives designers flexibility
in preventing bus contention in their system.
BYTE WRITE:
A low pulse on the WE or CE input with CE or WE low (respectively)
and OE high initiates a write cycle. The address is latched on the falling edge of CE
or WE, whichever occurs last. The data is latched by the first rising edge of CE or
WE. Once a byte write has been started it will automatically time itself to completion.
Once a programming operation has been initiated and for the duration of t
WC
, a read
operation will effectively be a polling operation.
PAGE WRITE:
The page write operation of the AT28C010-12DK allows 1 to 128
bytes of data to be written into the device during a single internal programming
period. A page write operation is initiated in the same manner as a byte write; the
first byte written can then be followed by 1 to 127 additional bytes. Each successive
byte must be written within 150
µs
(t
BLC
) of the previous byte. If the t
BLC
limit is
exceeded the AT28C010-12DK will cease accepting data and commence the
internal programming operation. All bytes during a page write operation must reside
on the same page as defined by the state of the A7 - A16 inputs. For each WE high
to low transition during the page write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within the page are to be
written. The bytes may be loaded in any order and may be altered within the same
load period. Only bytes which are specified for writing will be written; unnecessary
cycling of other bytes within the page does not occur.
DATA POLLING:
The AT28C010-12DK features DATA Polling to indicate the end of
a write cycle. During a byte or page write cycle an attempted read of the last byte
written will result in the complement of the written data to be presented on I/O7.
Once the write cycle has been completed, true data is valid on all outputs, and the
next write cycle may begin. DATA Polling may begin at anytime during the write
cycle.
TOGGLE BIT:
In addition to DATA Polling the AT28C010-12DK provides another
method for determining the end of a write cycle. During the write operation,
successive attempts to read data from the device will result in I/O6 toggling between
one and zero. Once the write has completed, I/O6 will stop toggling and valid data
will be read. Reading the toggle bit may begin at any time during the write cycle.
DATA PROTECTION:
If precautions are not taken, inadvertent writes may occur
during transitions of the host system power supply. Atmel has incorporated both
hardware and software features that will protect the memory against inadvertent
writes.
HARDWARE PROTECTION:
Hardware features protect against inadvertent writes
to the AT28C010-12DK in the following ways: (a) V
CC
sense – if V
CC
is below 3.8V
(typical) the write function is inhibited; (b) V
CC
power-on delay – once V
CC
has
reached 3.8V the device will automatically time out 5 ms (typical) before allowing a
write: (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write
cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a write cycle.
SOFTWARE DATA PROTECTION:
A software controlled data protection feature
has been implemented on the AT28C010-12DK. When enabled, the software data
protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled
or disabled by the user; the AT28C010-12DK is shipped from Atmel with SDP
disabled.
•
•
•
•
•
•
•
•
3
4259A–AERO–06/03
•
SDP is enabled by the host system issuing a series of three write commands; three
specific bytes of data are written to three specific addresses (refer to Software Data
Protection Algorithm). After writing the 3-byte command sequence and after t
WC
the
entire AT28C010-12DK will be protected against inadvertent write operations. It
should be noted, that once protected the host may still perform a byte or page write
to the AT28C010-12DK. This is done by preceding the data to be written by the
same 3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable command sequence is issued.
Power transitions do not disable SDP and SDP will protect the AT28C010-12DK
during power-up and power-down conditions. All command sequences must
conform to the page write timing specifications. The data in the enable and disable
command sequences is not written to the device and the memory addresses used in
the sequence may be written with data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command
sequence will start the internal write timers. No data will be written to the device;
however, for the duration of t
WC
, read operations will effectively be polling
operations.
DEVICE IDENTIFICATION:
An extra 128 bytes of EEPROM memory are available
to the user for device identification. By raising A9 to 12V
±
0.5V and using address
locations 1FF80H to 1FFFFH the bytes may be written to or read from in the same
manner as the regular memory array.
OPTIONAL CHIP ERASE MODE:
The entire device can be erased using a 6-byte
software code. Please see Software Chip Erase application note for details.
•
•
•
•
DC and AC Operating
Range
AT28C010-12DK-12
Operating
Temperature (Case)
V
CC
Power Supply
Mil.
-55°C - 125°C
5V
±
10%
Operating Modes
Mode
Read
Write
(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Notes:
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms
CE
V
IL
V
IL
V
IH
X
X
X
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
WE
V
IH
V
IL
X
V
IH
X
X
High Z
I/O
D
OUT
D
IN
High Z
4
AT28C010-12DK
4259A–AERO–06/03
AT28C010-12DK
Electrical Characteristics
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC
V
IL
V
IH
V
OL
V
OH1
V
OH2
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
I
OL
= 2.1 mA
I
OH
= -400
µA
I
OH
= -100
µA;
V
CC
= 4.5V
2.4
4,2
2.0
0.45
Condition
V
IN
= 0V to V
CC
+ 1V
V
I/O
= 0V to V
CC
CE = V
CC
- 0.3V to V
CC
+ 1V
CE = 2.0V to V
CC
+ 1V
f = 5 MHz; I
OUT
= 0 mA
Min
Max
10
10
300
3
80
0.8
Units
µA
µA
µA
mA
mA
V
V
V
V
V
5
4259A–AERO–06/03
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