Preliminary Technical Data
FEATURES
Low Power, 24-Bit Sigma-Delta ADC with In-
Amp and Embedded Reference (6 Channel)
AD7794
APPLICATIONS
Temperature measurement
Pressure measurement
Weigh scales
Six Differential Analog Inputs
Low Noise Programmable Gain Instrumentation-Amp
RMS noise: 80 nV (Gain = 64)
Bandgap Reference with 5 ppm/ C Drift typ
Power
Supply: 2.7 V to 5.25 V operation
Normal: 400 µA typ
Power-down: 1 µA max
Update Rate: 4 Hz to 500 Hz
Simultaneous 50 Hz/60 Hz Rejection
Internal Clock Oscillator
Reference Detect
Programmable Current Sources (10 µA/200 µA/1 mA)
On-Chip Bias Voltage Generator
100 nA Burnout Currents
Low Side Power Switch
Independent Interface Power Supply
24-Lead TSSOP Package
GENERAL DESCRIPTION
The AD7794 is a low power, complete analog front end for
low frequency measurement applications. It contains a low
noise 24-bit ∑-∆ ADC with six differential inputs. The on-chip
low noise instrumentation amplifier means that signals of small
amplitude can be interfaced directly to the ADC.
The device contains a precision low noise, low drift internal
reference for absolute measurements. An external reference can
also be used if ratiometric measurements are required. Other
on-chip features include programmable excitation current
sources and a bias voltage generator for temperature applica-
tions along with 100 nA burnout currents. For pressure and
weighscale applications, a low-side power switch is available to
power down the bridge between conversions to minimize the
power consumption of the system. The device can be operated
with the internal clock or, alternatively, an external clock can be
used if synchronizing several devices. The output data rate
from the part is software programmable and can be varied from
4 Hz to 500 Hz.
The part operates with a power supply from 2.7 V to 5.25 V. It
consumes a current of 450 uA maximum and is housed in a 24-
lead TSSOP package.
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
FUNCTIONAL BLOCK DIAGRAM
GND
VBIAS
AIN1(+)
AIN1(-)
AIN2(+)
AIN2(-)
AIN3(+)
AIN3(-)
AIN5(+)/IOUT2
AIN5(-)/IOUT1
AIN6(+)/P1
AIN6(-)/P2
PSW
GND
CLK
VDD
BANDGAP
REFERENCE
GND
IN-AMP
MUX
SIGMA DELTA
ADC
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
REFERENCE
DETECT
AVDD
AIN4(+)/REFIN2(+) REFIN1(+) AIN4(-)/REFIN2(-)
REFIN1(-)
GND
VDD
TEMP
SENSOR
INTERNAL
CLOCK
AD7794
DVDD
REV.PrE
6/04.
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD7794
TABLE OF CONTENTS
AD7794—Specifications.................................................................. 3
Timing Characteristics
,
.................................................................... 9
Absolute Maximum Ratings.......................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 14
On-chip Registers ........................................................................... 15
Communications Register (RS2, RS1, RS0 = 0, 0, 0) .............. 15
Status Register (RS2, RS1, RS0 = 0, 0, 0; Power-on/Reset =
0x88)............................................................................................. 16
Mode Register (RS2, RS1, RS0 = 0, 0, 1; Power-on/Reset =
0x000A)........................................................................................ 16
Configuration Register (rs2, RS1, RS0 = 0, 1, 0; Power-
on/Reset = 0x0710) .................................................................... 18
Data Register (RS2, RS1, RS0 = 0, 1, 1; Power-on/Reset =
0x000000) .................................................................................... 20
ID Register (RS2, RS1, RS0 = 1, 0, 0; Power-on/Reset = 0xxF)
....................................................................................................... 20
IO Register (RS2, RS1, RS0 = 1, 0, 1; Power-on/Reset = 0x00)
....................................................................................................... 20
OFFSET Register (RS2, RS1, RS0 = 1, 1, 0; Power-on/Reset =
0x800000) .................................................................................... 21
Preliminary Technical Data
FULL-SCALE Register (RS2, RS1, RS0 = 1, 1, 1; Power-
on/Reset = 0x5xxxx5) ................................................................ 21
ADC Circuit Information.............................................................. 22
Overview ..................................................................................... 22
Noise Performance ..................................................................... 22
Digital Interface .......................................................................... 23
Single Conversion Mode ....................................................... 24
Continuous Conversion Mode............................................. 24
Continuous Read Mode ........................................................ 25
Circuit Description......................................................................... 26
Analog Input Channel ............................................................... 26
Bipolar/Unipolar Configuration .............................................. 26
Data Output Coding .................................................................. 26
Reference ..................................................................................... 26
V
DD
Monitor ................................................................................ 27
Grounding and Layout .............................................................. 27
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
REV.PrE, June 2004: Initial Version
REV.PrE 6/04 | Page 2
Preliminary Technical Data
AD7794—SPECIFICATIONS
1
AD7794
Table 1. (AV
DD
= 2.7 V to 5.25 V; DV
DD
= 2.7 V to 5.25 V; GND = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
Parameter
AD7794 (CHOP ENABLED)
Output Update Rate
No Missing Codes
2
Resolution (pk – pk)
Output Noise and Update Rates
Integral Nonlinearity
Offset Error
3
Offset Error Drift vs. Temperature
4
Full-Scale Error
3, 5
Gain Drift vs. Temperature
4
Power Supply Rejection
ANALOG INPUTS
Differential Input Voltage Ranges
Absolute AIN Voltage Limits
2
Unbuffered Mode
Buffered Mode
In-Amp Enabled
Common Mode Voltage
Analog Input Current
Buffered Mode or In-Amp Enabled
Average Input Current
2
Average Input Current Drift
Unbuffered Mode
Average Input Current
Average Input Current Drift
Normal Mode Rejection
Internal Clock
@ 50 Hz, 60 Hz
@ 50 Hz
@ 60 Hz
External Clock
@ 50 Hz, 60 Hz
@ 50 Hz
@ 60 Hz
Common Mode Rejection
@DC
@ 50 Hz, 60 Hz
2
@ 50 Hz, 60 Hz
2
2
AD7794B
4
500
24
16
19
See Tables in ADC
Description
±15
±25
±3
±10
±10
±0.5
±3
90
±REFIN/Gain
Unit
Hz min nom
Hz max nom
Bits min
Bits p-p
Bits p-p
Test Conditions/Comments
Settling Time = 2/Output Update Rate
f
ADC
≤125 Hz
Gain = 128, 16.6 Hz Update Rate, V
REF
= 2.5 V
Gain = 1, 16.6 Hz Update Rate, V
REF
= 2.5 V
ppm of FSR max
ppm of FSR max
µV typ
nV/°C typ
µV typ
ppm/°C typ
ppm/°C typ
dB min
V nom
3.5 ppm typ. Gain = 1 to 32
5 ppm typ, Gain = 64 or 128
Gain = 1 or 2
Gain = 4 to 128
100 dB typ, AIN = FS/2
REFIN = REFIN(+) – REFIN(–) or Internal Reference,
Gain = 1 to 128
Gain = 1 or 2
Gain = 1 or 2
Gain = 4 to 128
Gain = 4 to 128
GND – 30 mV
AV
DD
+ 30 mV
GND + 100 mV
AV
DD
– 100 mV
GND + 300 mV
AV
DD
– 1.1
0.5
V min
V max
V min
V max
V min
V max
V min
±200
±2
±400
±50
1
pA max
pA/°C typ
nA/V typ
pA/V/°C typ
nA max
Gain = 1 or 2
Input current varies with input voltage.
AIN6(+) / AIN6(-)
70
84
90
80
94
90
90
100
100
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
6
90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
6
100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000
6
90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
6
100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
6
100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000
6
AIN = +FS/2
FS[3:0] = 1010
6
50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
6
50 ± 1 Hz (FS[3:0] = 1001
6
), 60 ± 1 Hz (FS[3:0] =
1000
6
)
REV.PrE 6/04 | Page 3
AD7794
Parameter
REFERENCE INPUT
Internal Reference Initial Accuracy
Internal Reference Drift
Internal Reference Noise
External REFIN Voltage
Reference Voltage Range
2
Absolute REFIN Voltage Limits
2
Preliminary Technical Data
AD7794B
1.17 ±0.01%
5
15
2
2.5
0.1
AV
DD
GND – 30 mV
AV
DD
+ 30 mV
400
±0.03
Same as for Analog
Inputs
Same as for Analog
Inputs
0.3
0.65
Unit
V min/max
ppm/°C typ
ppm/°C max
µV RMS
V nom
V min
V max
V min
V max
nA/V typ
nA/V/°C typ
Test Conditions/Comments
Gain = 1, Update Rate = 16.6 Hz. Includes ADC
Noise.
REFIN = REFIN(+) – REFIN(–)
Average Reference Input Current
Average Reference Input Current Drift
Normal Mode Rejection
2
Common Mode Rejection
Reference Detect Levels
V min
V max
NOXREF Bit Inactive if VREF < 0.3 V
NOXREF Bit Active if VREF > 0.65 V
REV.PrE 6/04 | Page 4
Preliminary Technical Data
Parameter
AD7794 (CHOP DISABLED)
Output Update Rate
No Missing Codes
2
Resolution
Output Noise and Update Rates
Integral Nonlinearity
Offset Error
3
Offset Error Drift vs. Temperature
4
Full-Scale Error
3, 5
Gain Drift vs. Temperature
4
Power Supply Rejection
ANALOG INPUTS
Differential Input Voltage Ranges
Absolute AIN Voltage Limits
2
Unbuffered Mode
Buffered Mode
In-Amp Enabled
Common Mode Voltage
Analog Input Current
Buffered Mode or In-Amp Enabled
Average Input Current
2
Average Input Current Drift
Unbuffered Mode
Average Input Current
Average Input Current Drift
Normal Mode Rejection
Internal Clock
@ 50 Hz, 60 Hz
@ 50 Hz
@ 60 Hz
External Clock
@ 50 Hz, 60 Hz
@ 50 Hz
@ 60 Hz
Common Mode Rejection
@DC
@ 50 Hz, 60 Hz
2
@ 50 Hz, 60 Hz
2
2
AD7794
AD7794B
4
500
24
15.5
18.5
See Tables in ADC
Description
±15
±25
±200/Gain
±200/Gain
±10
±0.5
±3
80
±REFIN/Gain
Unit
Hz min nom
Hz max nom
Bits min
Bits p-p
Bits p-p
Test Conditions/Comments
Settling Time = 1/Output Update Rate
f
ADC
≤125 Hz
Gain = 128, 16.6 Hz Update Rate, V
REF
= 2.5 V
Gain = 1, 16.6 Hz Update Rate, V
REF
= 2.5 V
ppm of FSR max
ppm of FSR max
µV typ
nV/°C typ
µV typ
ppm/°C typ
ppm/°C typ
dB min
V nom
3.5 ppm of FSR typ. Gain = 1 to 32
5 ppm of FSR typ, Gain = 64 or 128
Without Calibration
Gain = 1 or 2
Gain = 4 to 128
100 dB typ, AIN = FS/2
REFIN = REFIN(+) – REFIN(–) or Internal Reference,
Gain = 1 to 128
Gain = 1 or 2
Gain = 1 or 2
Gain = 4 to 128
Gain = 4 to 128
GND – 30 mV
AV
DD
+ 30 mV
GND + 100 mV
AV
DD
– 100 mV
GND + 100 mV
AV
DD
– 1.1
0.5
V min
V max
V min
V max
V min
V max
V min
±200
±2
±400
±50
1
pA max
pA/°C typ
nA/V typ
pA/V/°C typ
nA max
Gain = 1 or 2
Input current varies with input voltage.
AIN6(+) / AIN6(-)
60
80
90
60
94
90
80
80
80
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
70 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
6
90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
6
100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000
6
70 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
6
100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
6
100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000
6
AIN = +FS/2
FS[3:0] = 1010
6
50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
6
50 ± 1 Hz (FS[3:0] = 1001
6
), 60 ± 1 Hz (FS[3:0] =
1000
6
)
REFERENCE INPUT
Internal Reference Initial Accuracy
Internal Reference Drift
1.17 ±0.01%
5
15
V min/max
ppm/°C typ
ppm/°C max
REV.PrE 6/04 | Page 5
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