an Intel company
10 Gbit/s
Transmitter MUX
with Re-timing
GD16555B
Preliminary
General Description
GD16555B is a 9.95328 Gbit/s transmit-
ter chip for use in SDH STM-64 and
SONET OC-192 optical communication
systems.
GD16555B integrates all the main func-
tions of the transmitter, which is clock
generation, PLL circuits and multiplexer
in a single monolithic IC. Hence only an
external loop filter is required.
The main functions of GD16555B are
shown in the figure below. The clock
generation is made on-chip by a low
noise and tuneable 10 GHz VCO. The
VCO centre frequency is controlled by a
PLL with an external loop filter, allowing
the user to control the loop characteristic.
The clock synchronisation is controlled
by the Phase and Frequency Detector
with a 155 MHz or 622 MHz reference
clock input (package bonding option).
GD16555B multiplexes a 16 bit parallel
622 Mbit/s interface into a serial
9.9553 Gbit/s data stream.
The output of the MUX stage is retimed
by the 10 GHz clock and the output
driver is a
Current Mode Logic
(CML)
output with internal 50
W
termination re-
sistors.
The 16 bit wide parallel input interface is
differential CML with 50
W
internal load
termination, and with a 622 MHz clock
output mastering the timing at the STM-4
interface. The phase of the output clock
is selected in four phases: 0°, 90°, 180°,
and 270° by two select pins.
GD16555B is manufactured in a Silicon
Bipolar process.
GD16555B uses a single -5.2 V supply
voltage.
The power dissipation is 2 W, typical.
Features
l
On-chip low noise 10 GHz VCO with
a wide tuning range.
Automated capture of the VCO
frequency by a true phase and
frequency detector.
Retiming of MUX stage output with
10 GHz clock.
Clock failure detection NLDET.
16:1 MUX with differential 622 Mbit/s
CML data input.
CML data input with 50
W
internal
load termination.
622 MHz clock output for counter
clocking.
Clock output is selectable in four
phases: 0°, 90°, 180°, or 270°.
155 MHz or 622 MHz reference clock
input (package bonding option).
Single supply operation: -5.2 V
Low Power dissipation: 2 W (typ.).
Silicon Bipolar process.
68 pin Multi Layer Ceramic (MLC)
package.
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GD16555B is delivered in a
Multi Layer
Ceramic
(MLC) package, with internal
high-speed 50
W
transmission lines.
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DI0
DIN0
Parallel
Input Data
DI15
DIN15
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FF
16:1
Multiplexer
OUT
OUTN
CKOUT
CKOUTN
NLDET
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SEL1
SEL2
Timing
Control
Phase
Frequency
Detector
VCO
PCLT
POUT
PHIGH
PLOW
(only /155 vers.)
Applications
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VCTL
Telecommunication systems:
– SDH STM-64
– SONET OC-192.
Fibre optic test equipment.
Submarime transmission systems.
VCUR
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TCK
(*) = Package Bonding Option
S
E
L
3
(*)
R
E
F
C
K
R
E
F
C
K
N
VDD VDDO VDDA VEE
l
Data Sheet Rev.: 06
Functional Details
The main function of GD16555B is as
transmitter in STM-64 and SONET
OC-192 optical communication systems.
It integrates:
u
Voltage Controlled Oscillator
(VCO)
u
Phase and Frequency Detector
(PFD)
u
16:1 Multiplexer
u
Re-timing of output data.
with 50
W
internal resistors. The 16 bits
are multiplexed starting with DI0,
DI1...DI15.
All CML inputs have 50
W
internal termi-
nation resistors to a separated power pin
(VCMLT). With VCMLT connected to 0 V
all inputs are configured as CML inputs
(high/low equal 0/-0.4 V) or with VCMLT
connected to –2 V all inputs are confi-
gured as ECL compatible inputs (high/
low equal -0.8/ -1.8 V). With ECL inputs
the maximum current out of VCMLT is
400 mA and proper de- coupling of
VCMLT is required.
The select inputs (SEL1-2 and TCK) are
low-speed inputs, that can be connected
directly to the supply rails (0 / -5.2 V).
should always be terminated as shown in
Figure 1
also even though they are not
actively used in the PLL.
POUT is a high impendance input and
will be destroyed if connected directly
(low-ohmic, <25 kW) to -3.6 V to 0 V.
The Outputs
The output should be terminated exter-
nally with 50
W
at the receive end and
should be used differential. Both OUT
and OUTN are best terminated with the
same load resistor e.g. 50
W,
an asym-
metrically loading will decrease the per-
formance of the output due to reflections.
When terminated externally with 50
W,
the output voltage is 650 mV
PP
.
Both outputs
OUT/OUTN are not ESD
protected
and extra precautions should
be taken when handling the outputs (the
internal 50
W
resistor provides some
ESD hardness making the input low im-
pedance).
The clock outputs (CKOUT/N) are differ-
ential open collector outputs with a 8 mA
output current. They are terminated ex-
ternally with a resistor (R) to 0 V and the
output voltage swing is
V = -50 × 8 mA = -400 mV with R = 50
W.
Increasing the resistor increases the out-
put voltage swing and reduces the band-
width.
VCO
The VCO is an LC-type differential
10 GHz oscillator controlled by pin VCTL
and with a tuning range of
±5
%. The
VCO and the clock divider circuit gener-
ates the clock signal and load pulses
needed for multiplexing. It also generates
the output clock (CKOUT/ CKOUTN) and
the clock used in the phase and fre-
quency detector.
With the VCTL voltage at -3 V the VCO
frequency is fixed at 9.953 GHz and by
changing the voltage from 0 to –5.2 V the
frequency is controlled from 9 GHz to
10.2 GHz (See VCO Measurements on
page 17).
The modulation bandwidth of
VCTL is 90 MHz.
Loop Filter
The external loop filter is made using an
operational amplifier connected to output
pins (PHIGH and PLOW). The character-
istics of the phase lock loop are con-
trolled by the loop filter components
hence the op-amp is designed as an inte-
grator by a feedback capacitor and a re-
sistor. The gain-bandwidth of the op-amp
need to be larger than the required PLL
bandwidth in order not to limit it. The rec-
ommended op-amp is Analog Devices
(AD8042) with a gain-bandwidth of
160 MHz sufficient for PLL bandwidths
up to 50 MHz. The op-amp is used single
supplied by -5.2 V. See
Figure 1
for ap-
plication information.
The phase information from the PFD is
high frequency pulses at output pins
(PHIGH and PLOW). They are open col-
lector outputs with an 8 mA current drive
and are terminated externally by 220
W
to 0 V. A pre-filtering of the phase pulses
are applied by a parallel 10 pF capacitor.
The PCB layout of the external loop filter
and the connecting lines to PHIGH,
PLOW and VCTL are critical for the jitter
performance of the component. The art-
work for the op-amp and the passive
components should be placed very close
to the pins of GD16555B in order to have
connecting lines as short as possible.
Ideally the loop filter components are
placed on the opposite side of the PCB
directly underneath GD16555B. For more
layout suggestions see the 10 Gbit/s
evaluation board GD90244/255.
Alternatively the phase information is
also available at output pins (PCTL and
POUT) and they can be used with an ex-
ternal passive loop filter in applications
with a low PLL bandwidth (< 1 MHz) in-
stead of the above recommended active
loop filter. The PCTL and POUT pins
PFD
The PFD is made with digital set/reset
cells giving it a true phase and frequency
characteristic. The reference clock
(REFCK/REFCKN) to the PFD is 155 or
622 MHz (package bonding option, two
different product numbers).
A No Lock DETection signal (NLDET) is
provided as a status signal of the PLL. It
compares the VCO clock with the refer-
ence clock and is high whenever they dif-
fer. Using NLDET the situation of clock
failure, i.e. loss of signal can be detected.
The reference clock input has 50
W
inter-
nal termination resistors to pin VCMLT
and should be used differential.
The PLL will synchronize the 10 GHz
VCO to the external reference clock.
Noise from the reference clock, within the
PLL bandwidth will be multiplied and
added to the 10 Gbit/s output by the di-
vider ratio between VCO and reference
clock i.e. N = 16 / 64 or in terms of noise
as 20Log(16) = 24 dB or 36 dB. A low
noise reference clock with high frequency
stability is required in order to fulfill the
ITU-T jitter requirements.
Counter Clocking Timing
When the counter clocking timing is used
to control the timing between GD16555B
and the system ASIC, the output clock
(CKOUT/CKOUTN) is feed to the system
ASIC and clocks valid output data from
the ASIC into GD16555B. For easy inter-
facing of the system ASIC, the output
clock is selectable in four phases (0°,
90°, 180° or 270°) by SEL1-2. The maxi-
mum variation in the round trip delay
should be less than 1.1 ns when using
the counter clocking timing. This leaves
0.5 ns of valid data time for the
GD16555B . The roundtrip delay is the
total delay from clock in, to data out of
the system ASIC and the board delay for
clock and data. The setup and hold times
between CKOUT and input data are
specified for all four phases (see AC
Characteristics on
page 14).
The valid
time (e.g. the period of time where the in-
put data is not allowed to change) is
given by adding the setup and hold
times. The setup time is defined positive
before the rising edge of CKOUT. The
hold time is defined positive after the ris-
ing edge.
Inputs
The parallel input interface is 622 Mbit/s
differential
Current Mode Logic
(CML)
Data Sheet Rev.: 06
GD16555B
Page 2 of 20
If the variation is bigger than 1.1 ns an-
other type of different clocking timing is
needed e.g. forward clocking timing.
It is recommended to use all data inputs
differential for best performance.
Package
GD16555B is packaged in a 68 pin Multi
Layer Ceramic package with internal
50
W
transmission lines. The package is
a cavity-down type, which gives effective
cooling using the mounted heat
spreader.
The environment around the loop filter
and the 10 Gbit/s outputs is noise sensi-
tive and no noise generating lines are
allowed in this area.
The power supply to GD16555B should
be separated from other noise generation
components on the board and de-cou-
pled as shown on
Figure 2.
DC-DC con-
verters are only allowed on the same
board if proper noise filtering is applied.
Forward Clocking Timing
With the forward clocking timing both the
data and the clock is applied to
GD16555B with the clock as a reference
clock input (REFCK/REFCKN). See AC
Characteristics on
page 15.
It is impor-
tant for the jitter performance that the
clock is clean with no spurious frequency
noise and no noise injection from data
transitions. If the clock is generated from
a CMOS ASIC an additional PLL is
needed to clean up the clock before be-
ing applied as reference to GD16555B.
When using GD16555B with forward
clocking, the 622 MHz reference clock
option should be ordered.
External Circuits
The main external circuits needed to
make GD16555B work as a 10 Gbit/s
transmitter IC with re-timing and multi-
plexer are:
u
An active loop filter with op-amp
u
A reference clock at 155 MHz or
622 MHz with high frequency stability
u
Pull up resistors and de-coupling ca-
pacitors
Thermal Condition
The component dissipates 2.0 W with a
–5.2 V voltage supply and need forced
cooling with a heat sink thermally con-
nected to the heat spreader. The thermal
connection should ensure the case tem-
perature in the range from 0 to 70 °C with
the given ambient conditions e.g. tempe-
rature and air flow.
Mounting and Layout of PCB
The component can be mounted on a
standard FR4 epoxy printed circuit board
when special attention is taken in the lay-
out and in the mounting of the compo-
nent.
It is important for the performance of the
component that the leads of pin OUT and
OUTN (10 Gbit/s outputs) are made very
short (<1 mm) when mounted on the
board. Best way to make the leads short
are to cut a hole in the PCB and to mount
the component inside the hole. The
length of the two critical leads is reduced
to less than 0.5 mm whereas the rest of
the leads are kept at 2 - 4 mm in order
for mechanical stability. On the back side
the head spreader on the package is
thermally mounted to a metal block with
heat sink compound (see paragraph
“Mounting of Component on PCB” on
page 18).
In cases where the above mounting tech-
nical is not applicable, the component
can be mounted directly on the board
with bend leads accepting longer leads
for the 10 Gbit/s outputs. The component
is available with straight leads and with
gull wing leads (see the package outline
drawings on
page 19).
In the layout of the PCB the 10 Gbit/s in-
puts are connected with 50
W
Micro Strip
Lines
(MSL) to the high- speed connec-
tor. The MSL should be as short as pos-
sible (< 30 mm) with a plain and solid
ground plan below. The layout artwork
for the loop filter is placed preferable on
the opposite side of the component with
very short connections to the pins of
GD16555B. The 100
W
resistors and
10 pF capacitor connected from PHIGH
and PLOW to 0 V should be placed very
close to the package pin no. 50 and 53.
Power Noise Rejection
In a noisy environment special attention
must be taken as described above to op-
timize the jitter performance and to re-
duce the input sensitivity penalty from
injected noise. The
Power Supply Rejec-
tion Ratio
(PSRR) is improved by adding
a serial resistor (3.3 kW) and capacitor
(33 nF) from the positive input of the
op-amp to the power pin (VEE) as shown
in
Figure 1.
The Output Voltage Control
For the GD16555B version with a
155 MHz reference clock (GD16555B/
155-XX) a control signal (VCUR) is avail-
able at pin 41.
By controlling the voltage at VCUR the
DC output voltage at OUT/OUTN is ad-
justed in the range form 0.1 V to 0.8 V.
The VCUR can be operated from 0 V to
VEE.
For the GD16555B version with a
622 MHz reference clock (GD16555B/
622-XX) the control signal (VCUR) is not
available at pin 41.
GD16555B versus GD16255A
GD16555B is plug compatible and offers
the same or even better performance
compared with GD16255A. The pinouts
and the configurations of I/O´s are the
same except of the three differences as
described below:
u
No RESET pin
u
SEL 1/2 do not affect the timing rela-
tion between the reference clock and
the internal sampling of input data.
u
The values of one resistor and capa-
citor in the recommended loop filter.
Data Sheet Rev.: 06
GD16555B
Page 3 of 20
Application
1
0V
0V
VDDO / 51
VDD
0V
0V
0V
-5.2V
TCK / 45
VCMLT
SEL1 / 54
SEL2 / 56
61 / DI0
62 / DIN0
50
W
MSL
50
W
MSL
622 Mbit/s
CML Driver
0V
39 / DI15
50
W
MSL
10 Gbit/s
Output
VDD
50
W
MSL
50
W
MSL
50
W
MSL
OUT / 42
OUTN / 44
40 / DIN15
622 Mbit/s
CML Driver
GD16555B
15 / CKOUT
16 / CKOUTN
50
W
MSL
50
W
MSL
50W
50W
VDD
100nF
100nF
50
W
MSL
50
W
MSL
REFCK / 57
RECKN / 58
59 / NLDET
330
100nF
VDD
500W
500W
-5.2V
47 / PCTL
49 / POUT
100W
100nF
3.3kW
53 / PLOW
VCTL / 46
VEE 17/34/52
33nF
3.3kW
1kW
1kW
0.1
m
F
10pF
1kW
0V
0V
50 / PHIGH
-5.2V
0V
AD8042
+
-
-5.2V
220W
0.1
m
F
1kW
0V
Figure 1.
Application Information
2
VDD
VEE
VDDO
VEE
Pin4
C
C
Pin9
Pin14
C
Pin21
C
Pin26
C
Pin31
C
Pin36
C
Pin43
C
Pin48
C
Pin55
C
Pin60
C
Pin65
C
10
m
F
Pin51
C
C
Pin1
Pin35
C
VDDA
10
m
F
VCMLT
VEE
Pin18
C
Pin68
C
10
m
F
C is 10nF parallel with 100pF.
VEE pins 17/34/52
Figure 2.
De-coupling Supply
Data Sheet Rev.: 06
GD16555B
Page 4 of 20
10 Gbit/s Output Interface
GD16555B
0V
Driver
50W
50W
50
W
MSL
OUTN
OUT
-5.2V
Figure 3.
10 Gbit/s Outputs (OUT/OUTN), DC Coupled
GD16555B
0V
Driver
50W
50W
100nF
OUTN
50
W
MSL
OUT
-5.2V
Figure 4.
10 Gbit/s Outputs (OUT/OUTN), AC Coupled
Data Sheet Rev.: 06
GD16555B
Page 5 of 20
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