DS2705
SHA-1 Authentication Master
www.maxim-ic.com
GENERAL DESCRIPTION
The DS2705 provides the master side of a Secure
Hash Algorithm (SHA) based token authentication
scheme. Hardware-based SHA authentication allows
for security without the added cost and complexity of
a microprocessor-based system. Batteries and other
accessories are authenticated using a single contact
through the Dallas 1-WireÒ interface. Authentication
is performed on demand or automatically, with the
pass/fail status reported on open-drain output pins to
signal the charge system and/or drive LEDs. The
DS2705 stores a predetermined challenge-and-
response pair in nonvolatile (NV) EEPROM. The
DS2705 works in conjunction with Dallas Battery
Management SHA-1 token products, including the
DS2703 and DS2704.
PIN CONFIGURATION
CHAL
PASS
FAIL
1
2
3
4
8
7
6
5
VDD
MDQ
SDQ
VPP
VSS
mMAX
FEATURES
§
§
Initiates Challenge-and-Response
Authentication based on the SHA-1 Algorithm
Dallas 1-Wire Master/Slave Interface Operates
at Standard and Overdrive Speeds
Input and Output pins for Initiating Challenge
and Reporting Authentication Pass/Fail
Programmable Configuration
Operates from 2.5V to 5.5V Supply
Tiny
mMAX
Package (Pb-Free)
APPLICATIONS
Digital Cameras
Portable DVD and Media Players
Cradle and Accessory Chargers
Cell Phones/Smartphones
§
§
§
§
APPLICATION EXAMPLE
ORDERING INFORMATION
PART
DS2705U+
DS2705U+/T&R
TEMP RANGE
MARKING
DS2705
DS2705
PIN-PACKAGE
mMAX
DS2705U+ in Tape-and-Reel
-40°C to +85°C
-40°C to +85°C
+ Denotes lead-free package.
1-Wire is a registered trademark of Dallas Semiconductor.
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050506
DS2705: SHA-1 Authentication Master
ABSOLUTE MAXIMUM RATINGS
Voltage Range on All Pins (except VPP), Relative to V
SS
Voltage Range on V
PP
Pin, Relative to V
SS
Continuous Source Current, MDQ
Operating Temperature Range
Storage Temperature Range
Soldering Temperature
-0.3V to +5.5V
-0.3V to +18V
20mA
-40°C to +85°C
-55°C to +125°C
See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
DC ELECTRICAL CHARACTERISTICS
(2.5V
£
V
DD
£
5.5V, T
A
= -20°C to +85°C.)
PARAMETER
SYMBOL
I
DD1
Supply Current
I
DD2
I
DD3
Programming Voltage:
V
PP
Input Logic High:
MDQ, SDQ, CHAL
Input Logic Low:
MDQ, SDQ, CHAL
Output Logic Low: MDQ, SDQ
Output Logic Low:
PASS, FAIL
Pulldown:
V
PP
Pulldown: SDQ, CHAL
V
PP
V
IH
V
IL
V
OL1
V
OL2
I
PD1
I
PD2
I
OH
Pullup: MDQ
V
OH
Input Capacitance: MDQ, SDQ
C
IN
(Note 5)
Communication mode
(Note 6)
Computation mode
I
OH
= 2.0mA (Note 7)
0.25
CONDITIONS
Active mode,
MDQ low, I
O_MDQ
= 0
Active mode,
MDQ idle, I
O_MDQ
= 0
Sleep mode, I
O_MDQ
= 0 (Note 2)
Program pulse (Notes 1, 3)
(Note 1)
(Note 1)
I
OL
= 4mA (Note 1)
I
OL
= 10mA (Note 1)
300
0.125
2.5
14.5
1.8
0.6
0.4
0.4
MIN
TYP
MAX
2.5
90
1
130
2
15.0
UNITS
mA
mA
mA
V
V
V
V
V
mA
mA
mA
V
60
pF
V
DD
- 0.1
EEPROM RELIABILITY SPECIFICATION
(2.5V
£
V
DD
£
5.5V, T
A
= -20°C to +85°C.)
PARAMETER
EEPROM Write Time
EEPROM Write Endurance
SYMBOL
t
EEW
N
EEC
(Note 3)
(Notes 3, 4)
1,000
CONDITIONS
MIN
TYP
MAX
15
UNITS
ms
Cycles
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DS2705: SHA-1 Authentication Master
AC ELECTRICAL CHARACTERISTICS: MASTER 1-Wire INTERFACE
(2.5V
£
V
DD
£
5.5V, T
A
= -20°C to +85°C.)
PARAMETER
STANDARD BUS TIMING
Time Slot
Recovery Time
Write-0 Low Time
Write-1 Low Time
Read-Data Sample Window
Reset-Time Low
Presence-Detect High
Presence-Detect Low
OVERDRIVE BUS TIMING
Time Slot
Recovery Time
Write-0 Low Time
Write-1 Low Time
Read-Data Sample Window
Reset-Time Low
Presence-Detect High
Presence-Detect Low
t
MSLOT
t
MREC
t
MLOW0
t
MLOW1
t
MRDV
t
MRSTL
t
MPDH
t
MPDL
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
0.35
1.1
53
2
2
1
12
2
10.5
0.5
1.5
70
0.65
1.9
88
7
41
2.5
ms
ms
ms
ms
ms
ms
ms
ms
t
MSLOT
t
MREC
t
MLOW0
t
MLOW1
t
MRDV
t
MRSTL
t
MPDH
t
MPDL
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
1.05
4.0
510
2
2
7.5
90
10
88.5
1.5
5.5
680
2.25
7.0
850
75
400
12.5
ms
ms
ms
ms
ms
ms
ms
ms
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
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DS2705: SHA-1 Authentication Master
AC ELECTRICAL CHARACTERISTICS: SLAVE 1-Wire INTERFACE
(2.5V
£
V
DD
£
5.5V, T
A
= -20°C to +85°C.)
PARAMETER
STANDARD BUS TIMING
Time Slot
Recovery Time
Write-0 Low Time
Write-1 Low Time
Read-Data Valid
Reset-Time High
Reset-Time Low
Presence-Detect High
Presence-Detect Low
OVERDRIVE BUS TIMING
Time Slot
Recovery Time
Write-0 Low Time
Write-1 Low Time
Read-Data Valid
Reset-Time High
Reset-Time Low
Presence-Detect High
Presence-Detect Low
t
SLOT
t
REC
t
LOW0
t
LOW1
t
RDV
t
RSTH
t
RSTL
t
PDH
t
PDL
48
48
2
8
80
6
24
6
1
6
1
16
2
2
16
ms
ms
ms
ms
ms
ms
ms
ms
ms
t
SLOT
t
REC
t
LOW0
t
LOW1
t
RDV
t
RSTH
t
RSTL
t
PDH
t
PDL
480
480
15
60
960
60
240
60
1
60
1
120
15
15
120
ms
ms
ms
ms
ms
ms
ms
ms
ms
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
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DS2705: SHA-1 Authentication Master
AC ELECTRICAL CHARACTERISTICS
(2.5V
£
V
DD
£
5.5V, T
A
= -20°C to +85°C.)
PARAMETER
Programming Pulse Width
Programming Pulse Rise Time
Programming Pulse Fall Time
Strong Pullup Delay Time
Strong Pullup Period
Challenge Delay Time
Authentication Attempt Time
FAIL
Pin Pulse Frequency
SYMBOL
t
PPW
t
PPR
t
PPF
t
SPUD
t
SPUP
t
CHD
t
AAT
t
FPF
(Note 9)
FOM = 1, 50% duty cycle
24
45
61
1.5
2
(Note 8)
(Note 8)
CONDITIONS
MIN
17
0.5
0.5
2
34
65
5
5
10
48
85
490
2.5
TYP
MAX
UNITS
ms
ms
ms
ms
ms
ms
ms
Hz
Note 1:
Note 2:
All voltages are referenced to V
SS
.
IDD3 Sleep mode conditions:
CHAL pin inactive OR (CHAL active AND (PAA = 0 AND PPT = 00 AND FOM = 0 AND Initial Authentication sequence
complete))
[Above conditions disable the internal oscillator]
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Programming temperature range is T
A
= 0°C to 50°C.
5 years data retention at 70°C
If CHAL pin left unconnected, CHP bit = 0 required for an authentication attempt to be initiated on power up. See Table 1.
Typical Communication mode MDQ pullup behavior equivalent to 3kW resistor.
Typical Computation mode MDQ pullup behavior approximates a 50W resistor.
Exceeding maximum rise and fall time specifications may affect device reliability.
t
AAT
= Retries per Attempt x (264bits x 90ms + 3 x (
t
MRSTL
+
t
RSTH
) +
t
SPUD
) = [1 to 8] x (23.7ms + 3.54ms + 34ms)
MAX[7 retries]: 490ms, MIN[no retries]: 61ms with standard timings
t
RPDT
[defined in design documentation] = t
MRSTL
+ t
MRSTH
t
MPDL-MAX
= t
MRSTH-MIN
– t
MPDH-MAX,
represents the maximum presence pulse low time allowed from the slave.
Bus rise time of ~1ms required to settle to logic high by t
MRDV
after MDQ released at t
MLOW1
1.
2.
3.
4.
1-Wire Master timings based on ±25% clock tolerance from nominal.
PIN DESCRIPTION
PIN
mMAX
1
2
3
4
5
6
7
8
TDFN
1
2
3
4
5
6
7
8
SYMBOL
CHAL
PASS
FAIL
FUNCTION
Challenge Strobe Input Pin. Initiates authentication. Active level/edge set by CHP bit.
Authentication “PASS” Result Open-Drain Output Pin
Authentication “FAIL” Result Open-Drain Output Pin (Programmable As Low Or Pulse)
Supply Return Pin, GND Reference for Logic Signals
EEPROM Programming Voltage Input
Slave Serial interface Data I/O Pin. Bidirectional data transmit and receive at 16kbps or
143kbps. Bus master must provide a weak pullup.
Master Serial interface Data I/O Pin. Bidirectional data transmit and receive at 16kbps or
143kbps. Provides a weak pullup in communication mode and strong pullup in
computation mode.
Supply Input Pin. Bypass to
V
SS
with 0.1mF capacitor.
V
SS
V
PP
SDQ
MDQ
V
DD
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