Integrated
Circuit
Systems, Inc.
ICS950402
AMD - K8™ System Clock Chip
Recommended Application:
AMD K8 System Clock with AMD or VIA Chipset
Pin Configuration
*FS0/REF0 1
48 REF1/FS1*
Output Features:
VDDREF 2
47 GND
•
2 - Differential pair push-pull CPU clocks @
X1 3
46 VDDREF
3.3V
X2 4
45 REF2/FS2*
•
9 - PCICLK (Including 1 free running) @3.3V
GND 5
44 Reset#
*(PCICLK7/HTTCLK0)ModeA 6
43 VDDA
•
4 - Selectable PCICLK/HTTCLK @3.3V
*PCICLK8/HTTCLK1/ModeB 7
42 GND
•
1 - 48MHz, @3.3V fixed.
PCICLK9/HTTCLK2 8
41 CPUCLK8T0
•
1 - 24/48MHz @ 3.3V
VDDPCI 9
40 CPUCLK8C0
•
3 - REF @3.3V, 14.318MHz.
GND 10
39 GND
Features:
PCICLK10/HTTCLK3 11
38 VDDCPU
•
Programmable output frequency.
PCICLK11 12
37 CPUCLK8T1
PCICLK0 13
36 CPUCLK8C1
•
Programmable output divider ratios.
PCICLK1 14
35 VDDCPU
•
Programmable output rise/fall time.
GND 15
34 GND
•
Programmable output skew.
VDDPCI 16
33 GND
•
Programmable spread percentage for EMI
****PCICLK2 17
32 VDD
control.
****PCICLK3 18
31 48MHz/FS3**
•
Watchdog timer technology to reset system
VDDPCI 19
30 GND
if system malfunctions.
GND 20
29 AVDD48
PCICLK4 21
28 24_48MHz/Sel24_48#*~
•
Programmable watch dog safe frequency.
2
PCICLK5 22
27 GND
•
Support I C Index read/write and block read/
~*PCICLK_F/ModeC 23
26 SDATA
write operations.
~*(PCICLK6)PCI_STOP# 24
25 SCLK
•
Uses external 14.318MHz crystal.
48-Pin TSSOP/SSOP
•
Supports Hyper Transport Technology (HTTCLK).
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This Output has 2X Drive Strength
**** This Output has 2.3X Drive Strength
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
Functionality
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
100.90
133.90
168.00
202.00
100.20
133.50
166.70
200.40
150.00
180.00
210.00
240.00
270.00
233.33
266.67
300.00
HTT
MHz
67.27
66.95
67.20
67.33
66.80
66.75
66.68
66.80
60.00
60.00
70.00
60.00
67.50
66.67
66.67
75.00
PCI
MHz
33.63
33.48
33.60
33.67
33.40
33.38
33.34
33.40
30.00
30.00
35.00
30.00
33.75
33.33
33.33
37.50
REF (2:0)
CPU
DIVDER
Stop
CPUCLKC (1:0)
CPUCLKT (1:0)
SDATA
SCLK
FS (3:0)
MODE (A,B,C)
PCI_STOP#
24_48SEL#
Control
Logic
Config.
Reg.
PCI
DIVDER
Stop
PCICLK (6:0, 11)
PCICLK_F
X2
PCICLK/HTTCLK (3:0)
0700B—04/30/04
ICS950402
ICS950402
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PIN NAME
*FS0/REF0
VDDREF
X1
X2
GND
*(PCICLK7/HTTCLK0)ModeA
*PCICLK8/HTTCLK1/ModeB
PCICLK9/HTTCLK2
VDDPCI
GND
~PCICLK10/HTTCLK3
PCICLK11
PCICLK0
PCICLK1
GND
VDDPCI
****PCICLK2
****PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
~*PCICLK_F/ModeC
~*(PCICLK6)PCI_STOP#
SCLK
SDATA
GND
24_48MHz/Sel24_48#*~
AVDD48
GND
48MHz/FS3**
VDD
GND
GND
VDDCPU
CPUCLK8C1
CPUCLK8T1
VDDCPU
GND
CPUCLK8C0
CPUCLK8T0
GND
VDDA
Reset#
REF2/FS2*
VDDREF
GND
REF1/FS1*
PIN
TYPE
I/O
PWR
IN
OUT
PWR
I/O
I/O
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
I/O
PWR
PWR
OUT
OUT
I/O
I/O
IN
I/O
PWR
I/O
PWR
PWR
I/O
PWR
PWR
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
I/O
PWR
PWR
I/O
DESCRIPTION
Frequency select latch input pin / 14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
PCI clock output / Hyper Transport output / Mode selection pin, this input is activated by the
ModeB selection pin.
PCI clock output / Hyper Transport output / Mode selection latch input pin.
PCI clock output / Hyper Transport output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output / Hyper Transport output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Real time system reset signal for watchdog timer timeout. This signal is active low and
selected by Mode latch input / 3.3V PCI clock clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low / PCI clock
output, this output is activated by the Mode selection pin
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin.
PCI clock output, this output is activated by the Mode selection pin / Stops all PCICLKs
besides the PCICLK_F clocks at logic 0 level, when input low.
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
Ground pin.
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
Ground pin.
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
Power supply, nominal 3.3V
Ground pin.
Ground pin.
Supply for CPU clocks, 3.3V nominal
"Complimentary" clocks of differential 3.3V push-pull K8 pair.
"True" clocks of differential 3.3V push-pull K8 pair.
Supply for CPU clocks, 3.3V nominal
Ground pin.
"Complimentary" clocks of differential 3.3V push-pull K8 pair.
"True" clocks of differential 3.3V push-pull K8 pair.
Ground pin.
3.3V power for the PLL core.
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
14.318 MHz reference clock / Frequency select latch input pin.
Ref, XTAL power supply, nominal 3.3V
Ground pin.
14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength
**** This Output has 2.3X Drive Strength
0700B—04/30/04
2
ICS950402
General Description
The
ICS950402
is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary
clock signals for Clawhammer and Sledgehammer systems.
The
ICS950402
is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This
part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the
use of a serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency
setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and
enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to
0.1MHz increment.
Power Groups
Pin Number
AVDD
2
29
32
43
VDD
9
16, 19
35, 38
46
GND
5
27, 30
33
42
GND
10
15, 20
34, 39
47
PCI33_HT66outputs
PCI33 outputs
CPU outputs
REF
Description
Crystal
48MHz fixed,
Fix Analog, Fix Digital
CPU Master Clock, CPU Analog
Mode Functionality Tables
ModeA
0
0
1
1
ModeB
0
1
0
1
Pin6
HTTCLK0
ModeA
(Input Only)
PCICLK7
ModeA
(Input Only)
Pin7
HTTCLK1
HTTCLK1
PCICLK8
PCICLK8
Pin8
HTTCLK2
HTTCLK2
PCICLK9
PCICLK9
Pin11
PCICLK10
HTTCLK3
PCICLK10
PCICLK10
ModeC
0
1
Pin24
PCICLK6
PCI_STOP#
0700B—04/30/04
3
ICS950402
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
0700B—04/30/04
Not acknowledge
stoP bit
4
ICS950402
Table1: Frequency Selection Table
Bit5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit4
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit3
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit2
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
100.90
133.90
168.00
202.00
100.20
133.50
166.70
200.40
150.00
180.00
210.00
240.00
270.00
233.33
266.67
300.00
100.00
133.33
166.66
200.00
103.00
137.33
171.66
206.00
154.50
185.40
216.30
247.20
278.10
240.33
274.67
309.00
HTT
MHz
67.27
66.95
67.20
67.33
66.80
66.75
66.68
66.80
60.00
60.00
70.00
60.00
67.50
66.67
66.67
75.00
66.67
66.67
66.66
66.67
68.67
68.66
68.66
68.67
61.80
61.80
72.10
61.80
69.53
68.67
68.67
77.25
PCI
MHz
33.63
33.48
33.60
33.67
33.40
33.38
33.34
33.40
30.00
30.00
35.00
30.00
33.75
33.33
33.33
37.50
33.33
33.33
33.33
33.33
34.33
34.33
34.33
34.33
30.90
30.90
36.05
30.90
34.76
34.33
34.33
38.63
VCO
MHz
403.60
535.60
672.00
404.00
400.80
534.00
666.80
400.80
600.00
360.00
420.00
480.00
540.00
466.66
533.34
600.00
400.00
533.32
666.64
400.00
412.00
549.32
686.64
412.00
618.00
370.80
432.60
494.40
556.20
480.66
549.34
618.00
0700B—04/30/04
5
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