MB9DF125 - Atlas-L
MB9DF125 Series
General Description
MB9DF125 series is based on Cypress’s advanced ARM architecture (32-bit with instruction pipeline for RISC-like performance).
Improvements compared to the previous generation include significantly improved performance at higher frequency, reduced power
consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 128 MHz
operation frequency from an external resonator.
Note: ARM, Cortex, Thumb and CoreSight are the trademarks of ARM Limited in the EU and other countries.
Features
High-Performance/High Memory Content
ARM Cortex R4, 8KB D-Cache, 8KB I-Cache
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32-Bit ARMv7 architecture
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205 DMIPS
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1MB Internal Flash
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48KB Internal EEFlash (Data Flash)
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128KB Internal RAM with ECC
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Low Power
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Connectivity
2x CAN, 2 x LIN-USART, 3 x SPI, 1 x I2C, 2 x I2S
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Up to six Stepper Motor Control (SMC) outputs
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HS-SPI (memory mapped access)
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Switchable Power Domains
16KB Retention RAM
Flexible Clock Control
Debugging/Testing
ARM Coresight Debug and Trace
Debugging via JTAG Interface
Boundary Scan
5V capable IOs
Ta:
40 °C to +105 °C
Package: LQFP-176
Classical Automotive Instruments Cluster with pointers
Vehicle Controller for Virtual Cluster and Head Units in cards
Characteristics
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Safety Features/Security Features
Multiple Memory Production Units (MPU)
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Peripheral Protection Units (PPU)
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Timing Protection Unit (TPU)
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Cyclic Redundancy Checks (CRC of Flash, Cache and RAM)
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Watchdog
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Flash-, Debug- and Test-Security
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Secure Hardware Extension (SHE)
❐
Self-contained secure area
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Random Number generator
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Secure repository for cryptographic keys
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AES encryption/decryption block
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Applications
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Other Features
Up/Down Counters
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Programmable Pulse Generators
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Analog-to-Digital Converters - 50 channels
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Sound Generator
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Free Running/Reload Timers
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Real Time Clock (RTC)
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Input Capture Units, Output Compare units
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32 external Interrupts
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Errata:
For information on silicon errata, see
“Errata”
on page 395. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 002-05677 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 2, 2016
MB9DF125 - Atlas-L
Block Diagram
Controlgroup
EIC
NMI
RTC
SYSC
Watchdog
TPU
IRQ Control
Power Control
CLK_CFG_PD1
EIC0_INT00.... EIC0_INT31
Memories
EIC0_NMI
RTC_WOT
SYSC_CKOT
SYSC_CKOTX
CLK_CFG_PD4
EBI0_MDATA00i......EBI0_MDATA15i
EBI0_RDY
EBI_MDATA00o...EBI_MDATA15o
EBI_MAD00...EBI_MAD23
EBI_MDQM0, EBI_MDQM1
EBI_MWEX
EBI_MOEX
EBI_MCLK
EBI_MCASX
EBI_MRASX
EBI_MDWEX
EBI_MCKE
EBI_MNALE
EBI_MNCLE
EBI_MNWEX
EBI_MNREX
EBI_MCSX0...EBI_MCSX3
EBI_MCSX8
DBG0_CTL
DBG0_CLK
DBG0_TRACE0.... DBG0_TRACE7
X0
X1
MODE
X0A
X1A
RSTX
EEFlash
48K option
CLK_MEM_E_PD3
RetRAM
16K
TCMRAM
64K
CLK_MEM_E_PD3
CLK_DBG_PD2
EBI
Cortex R4
I−Cache
8K
128 MHz
MPU
12 ch
D−Cache
8K
SHE
Clock group
Oscillators
PLL’s
CSV/CLK−out
On−chip
Debug
CLK_TRACE_PD2
HS−SPI
(1 ch)
Memory
Map
BootROM
12K
ECC
TCFlash
1M
CLK_HPM_PD2
SRAM
48K
Trace
CLK_SYS_PD3
High Performance Matrix (HPM)
CLK_HPM_PD2
CLK_HPM_PD2
CLK_DMA_PD2
DMA0_DEOP_ACK0, DMA0_DEOP_ACK1
DMA0_DREQ0, DMA0_DREQ1
DMA0_DSTP0, DMA0_DSTP1
DMA0_DREQ_ACK0, DMA0_DREQ_ACK1
DMA0_DSTP_ACK0, DMA0_DSTP_ACK1
DMA0_DEOP0, DMA0_DEOP1
SPIn_CLKi
SPIn_DATA0i˘. SPIn_DATA3i
SPIn_SSi
SPIn_CLKo
SPIn_DATA[0]o˘. SPIn_DATA[3]o
SPIn_SSo
SPIn_SSO[1]˘. SPIn_SSO[3]
I2Sn_ECLK
I2Sn_SCKi
I2Sn_SDi
I2Sn_WSi
I2Sn_SDo
I2Sn_WSo
I2Sn_SCKo
CLK_PERI4_PD2
SG_SGA
SG_SGO
CLK_HPM_PD2
CLK_HPM_PD2
Peripheral Bus
Bridge 3
RLT
(10 ch)
PERI3_eRBUS
UDC
(1 ch)
Peripheral Bus
Bridge 4
DMA
(8 ch)
Peripheral Bus
Bridge 1
PERI5_AHB BUS
RLTn_TIN
RLTn_TOUT
UDC0_AIN0, UDC0_AIN1
UDC0_BIN0, UDC0_BIN1
UDC0_ZIN0, UDC0_ZIN1
UDC0_UDOT0
UDC0_UDOT1
GPIO0_00i˘... GPIO0_52i
GPIO0_62i,GPIO0_63i
GPIO1_00i˘...GPIO1_59i
GPIO2_00i˘... GPIO2_25i
GPIO0_00o˘GPIO0_52o
GPIO0_62o,GPIO0_63o
GPIO1_00o˘GPIO1_59o
GPIO2_00o˘GPIO2_25o
Peripheral Bus
Bridge 0
PERI4_SLAVE AHB BUS
SPI
(3 ch)
SG
(1 ch)
CAN
(2 ch)
PERI1_RBUS
USART
(1 ch)
I/O Timer
(4 ch)
FRT 16/17/18/19
ICU 18/19
OCU 16/17
16−bit PPG
(8 ch)
CLK_PERI1_PD2
CLK_PERI0_PD2
10−bit ADC
(50 ch)
I/O Timer
(4 ch)
FRT 0/1/2/3
ICU 2/3
OCU 0/1
USART
(1 ch)
I2C
(1 ch)
SMC
(6 ch)
16−bit PPG
(16 ch)
AVDD5
AVSS5
AVRH
ADC0_AN0..... ADC0_AN31
ADC0_EDGI
PERI0_RBUS
GPIO
(141 pins)
CLK_PERI3_PD2
I2S
(2 ch)
CANn_RX
CANn_TX
USART6_SCKi
USART6_SIN
USART6_SCKo
USART6_SOT
FRTn_FRCK
ICUn_IN0, ICUn_IN1
OTDn,OTDn_I,OTDn_G,OTDn_GI
USART0_SCKi
USART0_SIN
USART0_SCKo
USART0_SOT
I2C0_SCLi
I2C0_SDAi
I2C0_SCLo
I2C0_SDAo
SMCn_M1
SMCn_P1
SMCn_M2
SMCn_P2
PPG_ETRG0˘.. PPG_ETRG3
PPGn_PPGA
PPGn_PPGB
PPU
CRC
FRTn_FRCK
ICUn_IN0, ICUn_IN1
OTDn,OTDn_I,OTDn_G,OTDn_GI
PPG_ETRG0˘.. PPG_ETRG3
PPGA
PPGB
Power Domain
Power Domain
PD1
PD2
PD3
PD4
Modules
Clockgroup (Osc, PLL, CSV), Controlgroup (EIC, NMI, RTC, SYSC, WDG, TPU, IRQ Control, Power Control)
Peripheral bus 0 (ADC, FRT, ICU, OCU, USART, I2C, SMC, PPG), Peripheral bus 1 (SG, CAN, USART, FRT,
ICU, OCU, PPG), Peripheral bus 3 (RLT, UDC, GPIO, PPU), Peripheral bus 4 (SPI, I2S), On-Chip Debug,
Trace, SRAM, CRC
Cortex R4, SHE, MPU, I-Cache, D-Cache, TCM, TCFlash, EEFlash, TPU, BootROM, HS-SPI, EBI
RetRAM
Document Number: 002-05677 Rev. *B
Page 2 of 426
MB9DF125 - Atlas-L
Contents
MB9DF125 Features ......................................................... 4
Resource Distribution for Non-modulated Clock ....... 16
Lock/Unlock Values for Protection Units ................... 16
ID-Values for Module Identification Registers ........... 17
Package and Pin Assignment ....................................... 18
Package .................................................................... 18
I/O Pins and Functions .............................................. 26
I/O Pin Types............................................................. 68
IO Circuit Types......................................................... 74
Package .................................................................... 79
Interrupt / DMA................................................................ 81
NMI............................................................................ 91
DMA Overview .......................................................... 92
PPU ........................................................................... 97
Master ID................................................................... 98
I/O Map............................................................................. 99
Electrical Characteristics............................................. 340
Absolute Maximum Ratings..................................... 340
Recommended Operating Conditions ..................... 343
DC Characteristics .................................................. 344
AC Characteristics................................................... 351
Analog Digital Converter ......................................... 371
FLASH Memory Program/Erase Characteristics..... 373
RC Oscillator Frequency ......................................... 374
Procedures.................................................................... 376
Boundary Scan........................................................ 376
Flash Parallel Programming .................................... 378
Debug and Trace..................................................... 388
Handling Devices..........................................................
Preventing Latch-up ................................................
Handling of Unused Input Pins................................
Power Supply Pins ..................................................
Power on Sequence ................................................
Pin State During Active External Reset...................
Crystal Oscillator Circuit ..........................................
Notes on Using External Clock................................
Unused Sub Clock Signal........................................
Errata .............................................................................
Ordering Information....................................................
Appendix .......................................................................
Workaround for IRQ Unit Register
Read Timing Issue ..................................................
Workaround for Flash Erase Suspend
Internal ....................................................................
Workaround for IUNIT Interrupt Handling
Problem ...................................................................
Limitation Details Undefined Port Pin State
while Core Supply (VDD) is Unavailable .................
Multiple Analog Switches of SMC Port Pins
in Conducting State .................................................
Document History Page ...............................................
Sales, Solutions, and Legal Information ....................
Worldwide Sales and Design Support.....................
Products ..................................................................
PSoC® Solutions ....................................................
Cypress Developer Community...............................
Technical Support ...................................................
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Document Number: 002-05677 Rev. *B
Page 3 of 426
MB9DF125 - Atlas-L
MB9DF125 Features
Table 1. Overview
Feature
Max. Core frequency
DMA
TCFlash
EEFlash
AXI RAM (with ECC)
TCM RAM (with ECC)
RetRAM
Core has 4-way-associative cache
SHE
Boot-ROM
IRQ Ctrl
RTC (with auto calibration)
Source clock timer
RLT (Reload Timer) (32 bit)
FRT
ICU
OCU
PPG
SG (Sound Generator)
UDC (UpDown Counter)
CAN
USART (LIN-USART)
SPI
I2C
I2S
Quad - SPI
External bus
EIC (External Interrupts)
NMI (intern / extern)
SMC
ADC (10-bit)
Debug Trace
CRC
Package
ATLAS-L / QFP-176
128 MHz
8 channels
1 MB
48 KB
48 KB
64 KB
16 KB
I/D each 8KB
yes
16 KB
256
1 channel
4
10 channels
8 channels
8 channels
8 channels
24 channels
1 channel
2 channels
2 channels
2 channels
3 channels
1 channel
2 channels
1 channel
24-bit address/16-bit data
32 channels
32/1
6 channels
50 channels
(including 24 channels shared with SMC)
Standard 5-pin JTAG interface
4-bit and 8-bit trace data shared with re-
sources.
1 channel
QFP-176
ATLAS-L / QFP-240
128 MHz
8 channels
1 MB
48 KB
48 KB
64 KB
16 KB
I/D each 8KB
yes
16 KB
256
1 channel
4
10 channels
8 channels
8 channels
8 channels
24 channels
1 channel
2 channels
2 channels
2 channels
3 channels
1 channel
2 channels
1 channel
24-bit address/16-bit data
32 channels
32/1
6 channels
50 channels
(including 24 channels shared with SMC)
Standard 5-pin JTAG interface
4-bit, 8-bit and 16-bit trace data with
dedicated trace pins
1 channel
QFP-240
Document Number: 002-05677 Rev. *B
Page 4 of 426
MB9DF125 - Atlas-L
Table 2. Features
Feature
Technology
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Description
90nm CMOS with embedded flash
Cortex R4 CPU core
32-bit ARM architecture, dual-issue superscalar eight stage pipeline
ARMv7 and Thumb-2 instruction set compliant
Memory Protection Unit (MPU) with 12 regions
Two Tightly Coupled Memory (TCM) ports. 64-bit AXI slave port for access to TCMs
64-bit AXI master port
Vectored Interrupt Controller (VIC) port for faster interrupt processing
Single error correction, double error detection (SECDED) Error Correction Coding (ECC) for memory
error detection and correction
Instruction cache: 8KB 4-way set-associative
Data cache: 8KB 4-way set-associative
Up to 8 break-points and 8 watchpoints
ARM Coresight technology
Standard 5-pin JTAG interface
4-bit, 8-bit and 16-bit trace data width supported depending on package
Secure entry supported for debugger
External main clock of 4MHz (up to 8MHz under evaluation)
External sub clock (typical 32.768 kHz)
Embedded RC oscillator (typical 8/12 MHz, configurable)
Embedded Slow RC oscillator (typical 100 kHz)
On-chip Phase Locked Loop (PLL) clock multiplier for main clock, Spread Spectrum Clock Generation
(SSCG)
Stabilization timers for all source clocks
Clock supervision for all source clocks and PLL outputs
Reset generation for out-of-bound clock frequencies on input source clocks, or PLL output clocks
External Reset
Software triggered hard reset
Clock supervision resets
Watchdog
Low Voltage Detection reset
Software reset
Processor Subsystem
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Debug and Trace
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Clocks
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Clock Supervisor
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Resets
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Document Number: 002-05677 Rev. *B
Page 5 of 426
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