ASM5I23S04AF-1H-08-ST datasheet, PDF

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ASM5I23S04AF-1H-08-ST: DescriptionPLL Based Clock Driver, 23S Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8; Categorylogic logic; File Size430KB，15 Pages; ManufacturerPulseCore Semiconductor Corporation; Environmental Compliance

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ASM5I23S04AF-1H-08-ST Overview

PLL Based Clock Driver, 23S Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8

ASM5I23S04AF-1H-08-ST Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	PulseCore Semiconductor Corporation
package instruction	0.150 INCH, ROHS COMPLIANT, SOIC-8
Reach Compliance Code	unknown
series	23S
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G8
JESD-609 code	e3/e6
length	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN/TIN BISMUTH
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	3.91 mm
minfmax	133 MHz
Base Number Matches	1

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November 2006

ASMP5P23S04A

3.3V ‘SpreadTrak’ Zero Delay Buffer

rev 1.4

Features

•

Zero input - output propagation delay, adjustable

by capacitive load on FBK input.

Multiple configurations - Refer “ASM5P23S04A

Configurations Table”.

Input frequency range: 15 MHz to 133 MHz

Multiple low-skew outputs.

Output-output skew less than 200 pS.

Device-device skew less than 500 pS.

Two banks of two outputs each.

Less than 200 pS cycle-to-cycle jitter

•

(-1, -1H, -2, -2H).

FBK pin, and can be obtained from one of the outputs. The

input-to-output propagation delay is guaranteed to be less

than 250 pS, and the output-to-output skew is guaranteed

to be less than 200 pS.

The ASM5P23S04A has two banks of two outputs each.

Multiple ASM5P23S04A devices can accept the same input

clock and distribute it. In this case the skew between the

outputs of the two devices is guaranteed to be less than

500 pS.

The

ASM5P23S04A

(Refer

available

two

different

Available in space saving, 8-pin 150-mil SOIC

package.

3.3V operation.

Advanced 0.35µ CMOS technology.

Industrial temperature available.

‘SpreadTrak’.

configurations

“ASM5P23S04A

Configurations

Table). The ASM5P23S04A-1 is the base part, where the

output frequencies equal the reference if there is no

counter in the feedback path. The ASM5P23S04A-1H is

the high-drive version of the -1 and the rise and fall times

on this device are much faster.

The ASM5P23S04A-2 allows the user to obtain Ref and

1/2X frequencies on each output bank. The exact

configuration and output frequencies depend on which

output drives the feedback pin.

The ASM5P23S04A-2H is a high-drive version with REF/2

on both banks.

Functional Description

ASM5P23S04A is a versatile, 3.3V zero-delay buffer

designed

distribute

high-speed

clocks

PC,

workstation, datacom, telecom and other high-performance

applications. It is available in a 8-pin package. The part has

an on-chip PLL, which locks to an input clock, presented on

the REF pin. The PLL feedback is required to be driven to

Block Diagram

FBK

CLKA1

REF

PLL

CLKA2

Extra Divider (-2)

CLKB1

CLKB2

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008

•

Tel: 408-879-9077

•

Fax: 408-879-9018

www.pulsecoresemi.com

Notice: The information in this document is subject to change without notice.

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