APL6535
Two-Channel Supervisory IC
Features
•
•
•
•
•
•
•
2.6V to 5.5V Input Voltage Range
Low Quiescent Current : less than 50µA
High Accuracy Detection Threshold :
±
1.6%
Adjustable Undervoltage Lockout for Each
Supply
Active high PGOOD Output
Guaranteed PGOOD Valid to Falling V
CC
< 1V
VMON Glitch Immunity : 30µs
Lead Free Available (RoHS Compliant)
General Description
The APL6535 is a two channel supervisory IC designed
to monitor voltage supplies in mP and digital system.
This IC can supervise any positive voltage using an
external resistor divider to translate to a lower voltage
for comparison to the internal 0.633V reference. Once
any VMON input falls below 0.633V the PGOOD out-
put is pulled low, the hysteresis of the internal refer-
ence is 15mV. The PGOOD pin has an internal 20kW
pull-up to V
CC
making an external pull-up resistor
unnecessary. Each rail’ VMON point is independently
s
•
Applications
•
•
•
•
•
•
Graphics Cards
Portable Battery-Powered Equipment
µP Voltage Monitoring
Set-Top Boxes
Notebook Computer
Multiple Supply System
adjustable with a resistor divider. The PGOOD output
is guaranteed to be valid with IC bias lower than 1V.
This IC is designed to reject fast line transient glitches
30ms on VMON input. The PGOOD output is an open-
drain to allow ORing of multiple signals. If less than
four voltages are being monitored, connect the unused
VMON pins to V
CC
. The ENABLE input pin provides
for a reset of the PGOOD output when it is pulled
down below 0.5V. With an internal 10mA pull-up to
Pinouts
SOT-23-5 Top View
Vcc
GND
PGOOD
1
2
3
4
VMON2
5
VMON1
VCC, it can be signaled with common logic or pulled
to ground with a push button switch. APL6535 come
in a miniature SOT-23-5 package.
APL6535
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain
the latest version of relevant information to verify before placing orders.
Copyright
©
ANPEC Electronics Corp. Rev.
Rev. A.1 - May., 2005
1
www.anpec.com.tw
°
APL6535
Ordering and Marking Information
APL6535
Lead Free Code
Handling Code
Temp. Range
Package Code
A PL6535 :
535X
Package Code
B : SOT-23-5
Temp. Range
I : -40 to 85
°
C
Handling Code
TU : Tube
TR : Tape & Reel
Lead Free Code
L : Lead Free Device
Blank : Original Device
X - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte in plate termina-
tion finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations.
ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classifica-
tion at lead-free peak reflow temperature.
Pin Function Description
PIN
No.
1
3
2
Name
V
CC
PGOOD
GND
VMON1
VMON2
O
I/O
Supply Voltage
PGOOD is the AND function of all the VMON inputs being satisfied.
This is an open drain output and can be pulled high to the
appropriate level with an external resistor. Additionally a 20kO pull up
to V
CC
is provided internally.
Ground Connection
These inputs provide for a programmable monitored voltage
threshold referenced to an internal 0.633V reference. These inputs
have a 30
µ
s glitch filter to prevent transient upsets from being
recognized by PGOOD.
Description
4, 5
I
Copyright
©
ANPEC Electronics Corp. Rev.
Rev. A.1 - May., 2005
2
www.anpec.com.tw
APL6535
Electrical Characteristics
Unless Otherwise noted these specifications apply over full temperature, V
cc
= 3.3V, T
J
=- 40 °C to 85°C
Typical values refer to T
J
=25°C
Symbol
B BIAS
I
CC
I
CC
V
CC_L2H
V
CC_POR
PGOOD
PGpd
PGpu
Parameter
Test condition
APL6535
Unit
Min. Typ. Max.
40 400 µA
230 2000 µA
50 500 µA
50 500 µA
2.6
V
2.4
V
10
20
0
3
2
10
mA
K
Ω
100 mV
µs
µs
ns
Supply Current
(EN enable)
Supply Current
(EN disable)
V
CC
Power On
V
CC
Power On Reset
Pull-Down Current
Pull-Up Resistance
VMON > VMON_
L2H
VMON < VMON_
H2L
VMON > VMON_
L2H
VMON < VMON_
H2L
V
CC
low to high
V
CC
high to low
V
PGOOD
=0.5V
V
CC
= 1V
Last valid input =Vth to PG release
EN high to PG release
EN low to PG pulling low
T
J
=25°C
T
J
=-40
°
C to 85
°
C
V
PGI
Output Low
TPG del
Delay From VMON Rising
VMON
TPG del ENR Delay From EN Rising
TPG del ENF Delay From EN Falling
VMON Input
VMON
_H2L
Falling Threshold Voltage
VMON
_TC
Falling Threshold
Temperature Coeff.
Hysteresis Voltage
0.623 0.633 0.643 V
100
15
10
µV/
°
C
mV
mV
µs
VVMON
_HYS
VVMON
_RNG
Range
T
FIL
Glitch Filter Duration
VMON glitch to PGOOD low filter
30
Copyright
©
ANPEC Electronics Corp. Rev.
Rev. A.1 - May., 2005
4
www.anpec.com.tw
APL6535
Electrical Characteristics
Unless Otherwise noted these specifications apply over full temperature, V
cc
= 5V, T
J
=- 40 °C to 85°C
Typical values refer to T
J
=25°C
APL6535
Unit
Min. Typ. Max.
50 500 µA
230 2000 µA
60 600 µA
60 600 µA
2.6
V
2.4
V
10
20
0
5
2
10
mA
KΩ
100 mV
µs
µs
ns
Symbol
B BIAS
I
CC
I
CC
Parameter
Test condition
Supply Current
(EN Enable)
Supply Current
(EN Disable)
V
CC_L2H
V
CC
Power On
V
CC_POR
V
CC
Power On Reset
PGOOD
PGpd
Pull-Down Current
PGpu
Pull-Up Resistance
V
PGI
Output Low
TPG del
Delay From VMON Rising
VMON
TPG del ENR Delay From EN Rising
TPG del ENF Delay From EN Falling
VMON Input
VMON
_H2L
Falling Threshold Voltage
Falling Threshold
VMON
_TC
Temperature Coeff.
VVMON
_HYS
Hysteresis Voltage
VVMON
_RNG
Range
T
FIL
Glitch Filter Duration
VMON > VMON
_L2H
VMON < VMON
_H2L
VMON > VMON
_L2H
VMON < VMON
_H2L
V
CC
low to high
V
CC
high to low
V
PGOOD
=0.5V
V
CC
= 1V
Last valid input = Vth to PG
release
EN high to PG release
EN low to PG pulling low
T
J
=25°C
T
J
=-40°C to 85°C
0.623 0.633 0.643 V
100
15
10
30
µV/°C
mV
mV
µs
VMON glitch to PGOOD low filter
Copyright
©
ANPEC Electronics Corp. Rev.
Rev. A.1 - May., 2005
5
www.anpec.com.tw
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