BC41B143A-DS-002PD datasheet, PDF

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BC41B143A-DS-002PD: DescriptionBlueCore 4-ROM CSP EDR Single Chip Bluetooth v2.0 + EDR System; File Size766KB，89 Pages; ManufacturerETC

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BC41B143A-DS-002PD Overview

BlueCore 4-ROM CSP EDR Single Chip Bluetooth v2.0 + EDR System

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Device Features

Fully Qualified Bluetooth v2.0 + EDR System

Enhanced Data Rate (EDR) compliant with

v2.0 of specification for both 2Mbits/s and

3Mbits/s modulation modes

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Single Chip Bluetooth

v2.0 + EDR System

Product Data Sheet for

BC41B143A

September 2005

Full-speed Bluetooth Operation with Full

Piconet Support

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Scatternet Support

1.8V core, 1.7 to 3.6V I/O Split Rails

Ultra Low Power Consumption

Excellent Compatibility with Cellular

Telephones

Minimum External Components Required

Integrated 1.8V Linear Regulator

USB and UART Port to 3MBits/s

Support for 802.11 Co-existence

RoHS Compliant

General Description

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is a single-chip radio and

baseband IC for Bluetooth 2.4GHz systems

including EDR to 3Mbits/s.

With the on-chip CSR Bluetooth software stack it

provides a fully compliant Bluetooth system to

v2.0 + EDR of the specification for data and voice

communications.

Applications

Cellular Handsets

Personal Digital Assistants (PDAs)

Digital cameras and other high-volume consumer

products

Space critical applications

RAM

SPI

BlueCore4-ROM CSP is designed to reduce the number

of external components required. This ensures that

production costs are minimised.

The device incorporates auto-calibration and built-in

self-test (BIST) routines to simplify development, type

approval and production test. All hardware and device

firmware is fully compliant with the Bluetooth v2.0 + EDR

Specification (all mandatory and optional features).

To improve the performance of both Bluetooth and

802.11b/g co-located systems a wide range of

co-existence features are available including a variety of

hardware signalling: basic activity signalling and Intel

WCS activity and channel signalling.

UART/USB

ROM

RF IN

RF OUT

2.4

GHz

Radio

Baseband

DSP

I/O

PIO

MCU

PCM

XTAL

BlueCore4-ROM CSP System Architecture

BC41B143A-ds-002Pd

This material is subject to CSR’s non-disclosure agreement

Production Information

Page 1 of 89

Contents

Status Information ......................................................................................................................................... 7

Key Features .................................................................................................................................................. 8

CSP Package Information ............................................................................................................................. 9

3.1 BlueCore4-ROM CSP Pinout Diagram .................................................................................................... 9

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3.2 BC41B143AXX-IXF Device Terminal Functions .................................................................................... 10

Electrical Characteristics ............................................................................................................................ 13

4.1 Power Consumption .............................................................................................................................. 19

Radio Characteristics – Basic Data Rate ................................................................................................... 20

5.1 Temperature +20°C ............................................................................................................................... 20

5.1.1 Transmitter ................................................................................................................................. 20

5.1.2 Receiver ..................................................................................................................................... 22

5.2 Temperature -40°C................................................................................................................................ 24

5.2.1 Transmitter ................................................................................................................................. 24

5.2.2 Receiver ..................................................................................................................................... 24

5.3 Temperature -25°C................................................................................................................................ 25

5.3.1 Transmitter ................................................................................................................................. 25

5.3.2 Receiver ..................................................................................................................................... 25

5.4 Temperature +85°C ............................................................................................................................... 26

5.4.1 Transmitter ................................................................................................................................. 26

5.4.2 Receiver ..................................................................................................................................... 26

5.5 Temperature +105°C ............................................................................................................................. 27

5.5.1 Transmitter ................................................................................................................................. 27

5.5.2 Receiver ..................................................................................................................................... 27

Radio Characteristics – Enhanced Data Rate............................................................................................ 28

6.1 Temperature +20°C ............................................................................................................................... 28

6.1.1 Transmitter ................................................................................................................................. 28

6.1.2 Receiver ..................................................................................................................................... 29

6.2 Temperature -40°C................................................................................................................................ 30

6.2.1 Transmitter ................................................................................................................................. 30

6.2.2 Receiver ..................................................................................................................................... 31

6.3 Temperature -25°C................................................................................................................................ 32

6.3.1 Transmitter ................................................................................................................................. 32

6.3.2 Receiver ..................................................................................................................................... 33

6.4 Temperature +85°C ............................................................................................................................... 34

6.4.1 Transmitter ................................................................................................................................. 34

6.4.2 Receiver ..................................................................................................................................... 35

6.5 Temperature +105°C ............................................................................................................................. 36

6.5.1 Transmitter ................................................................................................................................. 36

6.5.2 Receiver ..................................................................................................................................... 37

Device Diagram ............................................................................................................................................ 38

Description of Functional Blocks ............................................................................................................... 39

8.1 RF Receiver........................................................................................................................................... 39

8.1.1 Low Noise Amplifier ................................................................................................................... 39

8.1.2 Analogue to Digital Converter .................................................................................................... 39

8.2 RF Transmitter....................................................................................................................................... 39

8.2.1 IQ Modulator .............................................................................................................................. 39

8.2.2 Power Amplifier .......................................................................................................................... 39

8.2.3 Auxiliary DAC ............................................................................................................................. 39

8.3 RF Synthesiser ...................................................................................................................................... 39

8.4 Power Control and Regulation............................................................................................................... 39

8.5 Clock Input and Generation ................................................................................................................... 40

8.6 Baseband and Logic .............................................................................................................................. 40

This material is subject to CSR’s non-disclosure agreement

Production Information

BC41B143A-ds-002Pd

Page 2 of 89

Contents

8.6.1 Memory Management Unit ......................................................................................................... 40

8.6.2 Burst Mode Controller ................................................................................................................ 40

8.6.3 Physical Layer Hardware Engine DSP....................................................................................... 40

8.6.4 RAM ........................................................................................................................................... 40

8.6.5 ROM........................................................................................................................................... 40

8.6.6 USB............................................................................................................................................ 41

8.6.7 Synchronous Serial Interface ..................................................................................................... 41

8.6.8 UART ......................................................................................................................................... 41

8.6.9 Audio PCM Interface .................................................................................................................. 41

8.7 Microcontroller ....................................................................................................................................... 41

8.7.1 Programmable I/O...................................................................................................................... 41

8.7.2 802.11 Coexistence Interface .................................................................................................... 41

CSR Bluetooth Software Stacks ................................................................................................................. 42

9.1 BlueCore HCI Stack .............................................................................................................................. 42

9.1.1 Key Features of the HCI Stack – Standard Bluetooth Functionality ........................................... 42

9.1.2 Key Features of the HCI Stack - Extra Functionality .................................................................. 44

9.2 BCHS Software ..................................................................................................................................... 45

9.3 Additional Software for Other Embedded Applications .......................................................................... 45

9.4 CSR Development Systems .................................................................................................................. 45

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10 Enhanced Data Rate .................................................................................................................................... 46

10.1 Enhanced Data Rate Baseband ............................................................................................................ 46

10.2 Enhanced Data Rate

π/4

DQPSK.......................................................................................................... 46

10.3 Enhanced Data Rate 8DPSK................................................................................................................. 47

11 Device Terminal Descriptions..................................................................................................................... 49

11.1 RF_A and RF_B .................................................................................................................................... 49

11.1.1 Transmit RF Power Control for Class 1 Applications ................................................................. 50

11.1.2 Control of External RF Components .......................................................................................... 51

11.2 External Reference Clock Input (XTAL_IN) ........................................................................................... 51

11.2.1 External Mode ............................................................................................................................ 51

11.2.2 XTAL_IN Impedance in External Mode ...................................................................................... 52

11.2.3 Clock Timing Accuracy............................................................................................................... 52

11.2.4 Clock Start-Up Delay.................................................................................................................. 52

11.2.5 Input Frequencies and PS Key Settings..................................................................................... 53

11.3 Crystal Oscillator (XTAL_IN, XTAL_OUT) ............................................................................................. 54

11.3.1 XTAL Mode ................................................................................................................................ 54

11.3.2 Load Capacitance ...................................................................................................................... 55

11.3.3 Frequency Trim .......................................................................................................................... 55

11.3.4 Transconductance Driver Model ................................................................................................ 56

11.3.5 Negative Resistance Model ....................................................................................................... 56

11.3.6 Crystal PS Key Settings ............................................................................................................. 57

11.3.7 Crystal Oscillator Characteristics ............................................................................................... 57

11.4 UART Interface...................................................................................................................................... 60

11.4.1 UART Bypass............................................................................................................................. 62

11.4.2 UART Configuration while RESETB is Active ............................................................................ 62

11.4.3 UART Bypass Mode................................................................................................................... 62

11.5 USB Interface ........................................................................................................................................ 63

11.5.1 USB Data Connections .............................................................................................................. 63

11.5.2 USB Pull-Up Resistor................................................................................................................. 63

11.5.3 Power Supply ............................................................................................................................. 63

11.5.4 Self-powered Mode .................................................................................................................... 63

11.5.5 Bus-powered Mode .................................................................................................................... 64

11.5.6 Suspend Current ........................................................................................................................ 65

11.5.7 Detach and Wake-Up Signalling ................................................................................................ 65

11.5.8 USB Driver ................................................................................................................................. 65

11.5.9 USB Compliance........................................................................................................................ 66

11.5.10

USB 2.0 Compatibility .......................................................................................................... 66

11.6 Serial Peripheral Interface ..................................................................................................................... 66

11.6.1 Instruction Cycle......................................................................................................................... 66

11.6.2 Writing to BlueCore4-ROM CSP ................................................................................................ 67

This material is subject to CSR’s non-disclosure agreement

Production Information

BC41B143A-ds-002Pd

Page 3 of 89

Contents

11.6.3 Reading from BlueCore4-ROM CSP.......................................................................................... 67

11.6.4 Multi-Slave Operation................................................................................................................. 67

11.7 Audio PCM Interface ............................................................................................................................. 68

11.7.1 PCM Interface Master/Slave ...................................................................................................... 68

11.7.2 Long Frame Sync....................................................................................................................... 69

11.7.3 Short Frame Sync ...................................................................................................................... 69

11.7.4 Multi Slot Operation.................................................................................................................... 70

11.7.5 GCI Interface.............................................................................................................................. 70

11.7.6 Slots and Sample Formats ......................................................................................................... 71

11.7.7 Additional Features .................................................................................................................... 71

11.7.8 PCM Timing Information ............................................................................................................ 72

11.7.9 PCM Slave Timing ..................................................................................................................... 74

11.7.10

PCM_CLK and PCM_SYNC Generation ............................................................................. 75

11.7.11

PCM Configuration .............................................................................................................. 76

11.8 I/O Parallel Ports ................................................................................................................................... 77

11.8.1 PIO Defaults for BlueCore4-ROM CSP...................................................................................... 77

11.9 I

C Master.............................................................................................................................................. 78

11.10

TCXO Enable OR Function ........................................................................................................ 78

11.11

Resetting BlueCore4-ROM CSP ................................................................................................ 79

11.11.1

Pin States during Reset ....................................................................................................... 79

11.11.2

Status after Reset ................................................................................................................ 80

11.12

Power Supply ............................................................................................................................. 80

11.12.1

Voltage Regulator ................................................................................................................ 80

11.12.2

Sequencing.......................................................................................................................... 80

11.12.3

Sensitivity to Disturbances................................................................................................... 80

12 Application Schematic................................................................................................................................. 81

13 Package Dimensions ................................................................................................................................... 82

14 Ordering Information ................................................................................................................................... 83

14.1 BlueCore4-ROM CSP............................................................................................................................ 83

15 Contact Information ..................................................................................................................................... 84

16 Document References ................................................................................................................................. 85

Terms and Definitions ........................................................................................................................................ 86

Document History ............................................................................................................................................... 89

_äìÉ`çêÉ»QJolj=`pm=bao mêçÇìÅí=a~í~=pÜÉÉí

BC41B143A-ds-002Pd

This material is subject to CSR’s non-disclosure agreement

Production Information

Page 4 of 89

Contents

List of Figures

Figure 3.1: BlueCore4-ROM CSP Package ............................................................................................................ 9

Figure 7.1: BlueCore4-ROM CSP Device Diagram for CSP Package .................................................................. 38

Figure 9.1: BlueCore HCI Stack ............................................................................................................................ 42

Figure 10.1: Basic Data Rate and Enhanced Data Rate Packet Types ................................................................ 46

Figure 10.2:

π/4

DQPSK Constellation Pattern ..................................................................................................... 47

Figure 10.3: 8DPSK Constellation Pattern ............................................................................................................ 48

Figure 11.1: Circuit RF_A and RF_B..................................................................................................................... 49

Figure 11.2: Internal Power Ramping.................................................................................................................... 50

Figure 11.3: TCXO Clock Accuracy ...................................................................................................................... 52

Figure 11.4: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting......................................... 53

Figure 11.5: Crystal Driver Circuit ......................................................................................................................... 54

Figure 11.6: Crystal Equivalent Circuit .................................................................................................................. 55

Figure 11.7: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency............................. 57

Figure 11.8: Crystal Driver Transconductance vs. Driver Level Register Setting .................................................. 58

Figure 11.9: Crystal Driver Negative Resistance as a Function of Drive Level Setting ......................................... 59

Figure 11.10: Break Signal.................................................................................................................................... 61

Figure 11.11: UART Bypass Architecture ............................................................................................................. 62

Figure 11.12: USB Connections for Self Powered Mode ...................................................................................... 64

Figure 11.13: USB Connections for Bus-Powered Mode ...................................................................................... 64

Figure 11.14: USB_DETACH and USB_WAKE_UP Signalling............................................................................. 65

Figure 11.15: Write Operation ............................................................................................................................... 67

Figure 11.16: Read Operation............................................................................................................................... 67

Figure 11.17: BlueCore4-ROM CSP as PCM Interface Master............................................................................. 68

Figure 11.18: BlueCore4-ROM CSP as PCM Interface Slave............................................................................... 69

Figure 11.19: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................. 69

Figure 11.20: Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 69

Figure 11.21: Multi Slot Operation with Two Slots and 8-bit Companded Samples .............................................. 70

Figure 11.22: GCI Interface................................................................................................................................... 70

Figure 11.23: 16-Bit Slot Length and Sample Formats ......................................................................................... 71

Figure 11.24: PCM Master Timing Long Frame Sync ........................................................................................... 73

Figure 11.25: PCM Master Timing Short Frame Sync........................................................................................... 73

Figure 11.26: PCM Slave Timing Long Frame Sync ............................................................................................. 74

Figure 11.27: PCM Slave Timing Short Frame Sync............................................................................................. 75

Figure 11.28: Example EEPROM Connection ...................................................................................................... 78

Figure 11.29: Example TXCO Enable OR Function .............................................................................................. 78

Figure 12.1: Application Circuit for CSP Package ................................................................................................. 81

Figure 14.1: BlueCore4-ROM CSP Package Dimensions..................................................................................... 82

_äìÉ`çêÉ»QJolj=`pm=bao mêçÇìÅí=a~í~=pÜÉÉí

BC41B143A-ds-002Pd

This material is subject to CSR’s non-disclosure agreement

Production Information

Page 5 of 89

BC41B143A-DS-002PD Related Products

	BC41B143A-DS-002PD	BC41B143AXX-IXB-E4
Description	BlueCore 4-ROM CSP EDR Single Chip Bluetooth v2.0 + EDR System	BlueCore 4-ROM CSP EDR Single Chip Bluetooth v2.0 + EDR System

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