HX6408
Advanced Information
HX6408
512k x 8 STATIC RAM
The 512K x 8 Radiation Hardened Static RAM is a high
performance 524,288 word x 8-bit static random access
memory with optional industry-standard functionality. It is
fabricated with Honeywell’s radiation hardened Silicon On
Insulator (SOI) technology, and is designed for use in low
voltage systems operating in radiation environments. The
RAM operates over the full military temperature range and
requires only a single 3.3 V ± 0.3V power supply. Power
consumption is typically <30 mW @ 1MHz in write mode,
<14 mW @ 1MHz in read mode, and is less than 5 mW
when in standby mode.
Honeywell’s enhanced RICMOS™(Radiation Insensitive
CMOS) SOI V technology is radiation hardened through the
use of advanced and proprietary design, layout and process
hardening techniques.
The RICMOS™ V low power process is a SOI CMOS
technology with an 80 Å gate oxide and a minimum
drawn feature size of 0.35
µm.
Additional features
include tungsten via and contact plugs, Honeywell’s
proprietary SHARP planarization process and a lightly
doped drain (LDD) structure for improved short
channel reliability. A seven transistor (7T) memory cell
is used for superior single event upset hardening,
while three layer metal power busing and the low
collection volume SOI substrate provide improved
dose rate hardening.
FEATURES
Fabricated with RICMOS™ V
Silicon On Insulator (SOI)
0.35 mm Process (L
eff
= 0.28 µm)
Total Dose
≥
3x10
5
and 1X10
6
rad(SiO
2
)
Neutron
≥1x10
cm
14
-2
No Latchup
Read/Write Cycle Times
≤20
ns, (3.3 V), -55 to 125°C
Typical Operating Power (3.3 V)
<14 mW @ 1MHz Read
<30 mW @ 1MHz Write
<5 mW Standby mode
Asynchronous Operation
CMOS Compatible I/O
Single Power Supply,
3.3 V ± 0.3 V
Operating Range is
-55°C to +125°C
36-Lead Flat Pack Package
Optional Low Power Sleep
Mode
Dynamic and Static Transient Upset
≥1x10
10
rad(Si)/s (3.3 V)
Dose Rate Survivability
≥1x10
12
rad(Si)/s
Soft Error Rate
≤1x10
-10
Upsets/bit-day (3.3 V)
1
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HX6408
Advanced Information
FUNCTIONAL DIAGRAM
36 LEAD FLAT PACK PINOUT
HX6408
Top View
Address
Decoder
A0
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
(NSL)
A18
A17
A16
A15
NOE
D4
D5
VSS
VDD
D6
D7
A14
A13
A12
A11
A10
NAS
An
Memory
Array
A1
A2
A3
A4
NWE
Timing \ Control
DQ(0:7)
WE • CS
NWE • CS
NCS
D0
D1
VDD
VSS
D2
D3
NSL
NCS
NOE
NWE 13
All controls must be enabled
for signal to pass.
# = number of buffers,
Default = 1
1 = enabled
Signal
#
Signal
A5 14
A6 15
A7 16
A8 17
A9 18
SIGNAL DEFINITIONS
A: 0-18
DQ: 0-7
NCS
Address input pins, which select a particular eight-bit word within the memory array.
Bidirectional data pins, which serve as data outputs during a read operation and as data inputs
during a write operation.
Negative chip select, when at a low level allows normal read or write operation. When at a high level
NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance
state. If this signal is not used it must be connected to VSS.
Negative write enable, when at a low level activates a write operation and holds the data output
drivers in a high impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance
state. When at a low level, the data output driver state is defined by NCS, NWE and NSL. This
signal is asynchronous.
Not sleep, when at a high level allows normal operation. When at a low level NSL forces the SRAM
to a precharge condition, holds the data output drivers in a high impedance state and disables all the
input buffers except the NCS and NOE input buffers. If this signal is not used it must be connected
to VDD. This signal is asynchronous. The HX6408 may be ordered without the sleep mode option
and pin 36 is then a NC.
NWE
NOE
NSL
2
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HX6408
Advanced Information
TRUTH TABLE
NCS
L
L
H
X
NSL
H
H
X
L
NWE
H
L
X
X
NOE
L
X
X
X
Mode
Read
Write
Deselected
Sleep
DQ
Data Out
Data In
High Z
High Z
X: VI = VIH or VIL,
NOE=H:
High Z output state maintained for NCS=X, NWE=X
RADIATION
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature
range after the specified total ionizing radiation dose.
All electrical and timing performance parameters will
remain within specifications. Total dose hardness is
assured by wafer level testing of process monitor
transistors and RAM product using 10 KeV X-ray.
Transistor gate threshold shift correlations have been
made between 10 KeV X-rays applied at a dose rate of
1x10
5
rad(SiO
2
)/min at T= 25°C and gamma rays
(Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under
recommended operating conditions. It is recommended
to provide external power supply decoupling capacitors
to maintain VDD voltage levels during transient events.
The SRAM will meet any functional or electrical
specification after exposure to a radiation pulse up to
the transient dose rate survivability specification, when
applied under recommended operating conditions.
Note that the current conducted during the pulse by the
RAM inputs, outputs, and power supply may
significantly exceed the normal operating levels. The
application design must accommodate these effects.
Neutron Radiation
The SRAM will meet any functional or timing
specification after exposure to the specified neutron
fluence under recommended operating or storage
conditions. This assumes an equivalent neutron energy
of 1 MeV.
Soft Error Rate
The SRAM is capable of meeting the specified Soft
Error Rate (SER), under recommended operating
conditions.
This hardness level is defined by the Adams 90%
worst case cosmic ray environment for
geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions. Fabrication with
the SOI substrate material provides oxide isolation
between adjacent PMOS and NMOS transistors and
eliminates any potential SCR latchup structures.
Sufficient transistor body tie connections to the p- and
n-channel substrates are made to ensure no
source/drain snapback occurs.
3
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HX6408
Advanced Information
RADIATION HARDNESS RATINGS (1)
Parameter
Total Dose
Transient Dose Rate Upset
Transient Dose Rate Survivability
Limits (2)
≥3X10
≥1X10
6
10
≥1X10
≥1X10
12
5
Units
rad(SiO
2
)
rad(Si)/s
rad(Si)/s
Test Conditions
T
A
=25°C
Pulse width
≤50
ns
VDD>3.6V, T
A
=25°C
Pulse width
≤50
ns, X-
ray,VDD=3.6V,
T
A
=25°C
T
A
= 85°C, Adams 90%
worst case environment
1MeV equivalent
energy, Unbiased,
T
A
=25°C
Soft Error Rate
Neutron Fluence
<1X10
-10
≥1X10
14
Upsets/bit-day
N/cm
2
(1)
(2)
Device will not latch up due to any of the specified radiation exposure conditions.
o
o
Operating conditions (unless otherwise specified): VDD=3.0V to 3.6V, TA=-55 C to 125 C
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VDD
VPIN
TSTORE
TSOLDER
PD
IOUT
VPROT
ΘJC
TJ
(1)
(2)
(3)
(4)
Parameter
Min
Supply Voltage Range (2)
Voltage on Any Pin (2)
Storage Temperature (Zero Bias)
Soldering Temperature (5 seconds)
Maximum Power Dissipation (3)
DC or Average Output Current
EST Input Protection Voltage (4)
Thermal Resistance (Jct-to-Case)
Junction Temperature
-0.5
-0.5
-65
Rating
Max
4.6
VDD+0.5
150
270
2.5
25
2
175
Units
V
V
°C
°C
W
mA
V
°C/W
°C
2000
36 Pin FP
Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is
not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
Voltage referenced to VSS.
RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this
specification.
Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DSEC certified lab.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
TA
VPIN
VDDRAMP
Parameter
Min
Supply Voltage (referenced to VSS)
Ambient Temperature
Voltage on Any Pin (referenced to VSS)
VDD Turn on ramp time
3.0
-55
-0.3
Description
Typ
Max
3.3
25
3.6
125
VDD+0.3
50
Units
V
°C
V
ms
4
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HX6408
Advanced Information
DC ELECTRICAL CHARACTERISTICS
Symbol
IDDSB
Parameter
Static Supply Current
TA=25°C
TA=125°C
Static Supply Current
Deselected
Dynamic Supply Current,
Selected (Write)
1 MHz
2 MHz
10 MHz
25 MHz
40 MHz
Dynamic Supply Current,
Selected (Read)
1 MHz
2 MHz
10 MHz
25 MHz
40 MHz
Dynamic Supply Current,
Deselected
Dynamic Supply Current,
Sleep
Input Leakage Current
Output Leakage Current
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
High-Level Output Voltage
Worst Case (1)
Min
Max
5
10
24
Units
Test Conditions
mA
mA
IDDOP3
IDDOPW
VDD=max, Iout=0mA,
Inputs Stable
VDD=max, Iout=0mA,
f=fmax, NSL=NCS=VIH (2)
9
18
89
160
260
mA/MHz
VDD=max, Iout=0mA,
NSL=VIH, NCS=VIL (1)
IDDOPR
IDDOP1
IDDOP2
II
IOZ
VIL
VIH
VOL
VOH
(1)
(2)
4
8
40
100
160
1.5
0.2
-5
-10
5
10
0.3xVDD
0.7xVDD
0.4
2.7
mA/MHz
VDD=max, Iout=0mA,
NSL=VIH, NCS=VIL (1)
mA
mA
µA
µA
V
V
V
V
VDD=max, Iout=0mA,
f=1MHz, NSL=VIH (2)
VDD=max, Iout=0mA,
f=1MHz, NSL=VIL (2)
Vss VI VDD
Vss VIO
VDD output = high Z
VDD=3.0V
VDD=3.6V
VDD=3.0V, IOL = 8mA
VDD=3.0V, IOH = 4mA
Worst case operating conditions: VDD=3.0V to 3.6V, -55°C to +125°C, post total dose at 25°C.
All inputs switching. DC average current.
CAPACITANCE (1)
Symbol
CI
CO
Parameter
Input Capacitance
Output Capacitance
Worst Case (1)
Min
Max
9
8
Units
pF
pF
Test Conditions
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
5
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