XR72L52 datasheet, PDF - EEWORLD Datasheet

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XR72L52: DescriptionTWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER; File Size3MB，480 Pages; ManufacturerExar [Exar Corporation]

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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FEBRUARY 2005

XRT72L52

TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

REV. 1.0.1

GENERAL DESCRIPTION

The XRT72L52, Two Channel DS3/E3 Framer IC is

designed to accept user data from the Terminal

Equipment and insert this data into the payload bit-

fields within an outbound DS3/E3 Data Stream. Fur-

ther, the Framer is also designed to receive an in-

bound DS3/E3 Data Stream from the Remote Termi-

nal Equipment and extract out the user data.

The XRT72L52 DS3/E3 Framer device is designed to

support full-duplex data flow between Terminal Equip-

ment and an LIU (Line Interface Unit) IC. The Framer

Device will transmit, receive and process data in the

DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3-

ITU-T G.832 Framing Formats.

The XRT72L52 DS3/E3 Framer IC consists of a

Transmit section, Receiver section, Performance

Monitor Section and a Microprocessor interface.

The Transmit Section includes a Transmit Payload

Data Input Interface, a Transmit Overhead data Input

Interface Section, a Transmit HDLC Controller, a

Transmit DS3/E3 Framer block and a Transmit LIU

Interface Block which permits the Terminal Equip-

ment to transmit data to a remote terminal.

The Receive Section consists of a Receive LIU Inter-

face, a Receive DS3/E3 Framer, a Receive HDLC

Controller, a Receive Payload Data Output Interface,

and a Receive Overhead Data Interface which allows

the local terminal equipment to receive data from re-

mote terminal equipment.

The Microprocessor Interface is used to configure the

Framer IC in different operating modes and monitor

the performance of the Framer.

The Performance Monitor Sections consist of a large

number of Reset-upon-Read and Read-Only regis-

ters that contain cumulative and one-second statistics

that reflect the performance/health of the Framer IC/

system.

FEATURES

•

Transmits, Receives and Processes data in the

DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and

E3-ITU-T G.832 Framing Formats.

•

1 Channel HDLC Controller - Tx and Rx

•

Interfaces to all Popular Microprocessors

•

Integrated Framer Performance Monitor

•

Available in a 160 Pin PQFP package

•

3.3V Power Supply with 5V Tolerant I/O

•

Operating Temperature -40°C to +85°C

APPLICATIONS

•

Network Interface Units

•

CSU/DSU Equipment.

•

PCM Test Equipment

•

Fiber Optic Terminals

•

DS3/E3 Frame Relay Equipment

IGURE

1. B

LOCK

IAGRAM OF THE

XRT72L52

TRST

TestMode

NibbleIntf

TxOHEnable

TxOHClk

TxOHFrame

TxAISEn

TxOH

TxOHIns

Typical Channel n

Where n = 0 or 1

T3/E3

Transmit

Overhead

Interface

T3/E3 Transmit

Framer

T3/E3

transmit

Input

HDLC

controller

TxOHInd[n:0]

TxNibFrame[n:0]

TxFrame[n:0]

TxNibClk[n:0]

TxLnClk[n:0]

TxFrameRef[n:0]

TxNib[n:0]

TxSer[n:0]

TxLineClk[n:0]

TxPOS[n:0]

TxNEG[n:0]

LIU

Interface/

Controller

T3 FEAC & Data

Link Controller

Performance

Monitor

Interrupt

Controller

Interface

RxLineClk[n:0]

RxPOS[n:0]

RxNEG[n:0]

ExtLOS

A(11:0)

D(7:0)

ALE_AS

WR_R/W

RDY_DTCK

Reset

INT

MOTO

RD_DS

RxOHEnable[n:0]

RxOHClk[n:0]

RxOH[n:0]

RxRed[n:0]

RxOHFrame[n:0]

RxOOF[n:0]

T3/E3

Receive

Overhead

Interface

T3/E3 Receive

Framer

T3/E3

Receive

Output

HDLC

controller

RxClk[n:0]

RxOHind[n:0]

RxFrame[n:0]

RxNib[n:0]

RxSer[n:0]

RxOUTClk[n:0]

Exar

Corporation 48720 Kato Road, Fremont CA, 94538

•

(510) 668-7000

•

FAX (510) 668-7017

•

www.exar.com

TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52

REV. 1.0.1

TABLE OF CONTENTS

GENERAL DESCRIPTION................................................................................................. 1

FEATURES

................................................................................................................................................... 1

APPLICATIONS

............................................................................................................................................. 1

Figure 1. Block Diagram of the XRT72L52 ....................................................................................................................... 1

Figure 2. Pin Out of the XRT72L52 .................................................................................................................................. 2

ORDERING INFORMATION .............................................................................................. 2

TABLE OF CONTENTS .................................................................................................................................. I

PIN DESCRIPTIONS .......................................................................................................... 3

ELECTRICAL CHARACTERISTICS................................................................................ 22

BSOLUTE

AXIMUMS

............................................................................................................................... 22

DC E

LECTRICAL

HARACTERISTICS

........................................................................................................... 22

AC E

LECTRICAL

HARACTERISTICS

........................................................................................................... 22

AC E

LECTRICAL

HARACTERISTICS

ONT

.) .............................................................................................. 24

1.0 Timing Diagrams ................................................................................................................................ 28

Figure 3. Timing Diagram for Transmit Payload Input Interface, when the XRT72L52 is operating in both the DS3 and Loop-

Timing Modes .................................................................................................................................................. 28

Figure 4. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L52 is operating in both the DS3 and

Local-Timing Modes ........................................................................................................................................ 28

Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L52 is operating in both the DS3/

Nibble and Looped-Timing Modes................................................................................................................... 29

Figure 6. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L52 is operating in the DS3/Nibble

and Local-Timing Modes ................................................................................................................................. 29

Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) ..................................... 30

Figure 8. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) ..................................... 30

Figure 9. Transmit LIU Interface Timing - TxPOS and TxNEG are updated on the rising edge of TxLineClk ................ 31

Figure 10. Transmit LIU Interface Timing - TxPOS and TxNEG are updated on the falling edge of TxLineClk ............. 31

Figure 11. Receive LIU Interface timing - RxPOS and RxNEG are sampled on rising edge of RxLineClk..................... 32

Figure 12. Receive LIU Interface timing - RxPOS and RxNEG are sampled on falling edge of RxLineClk ................... 32

Figure 13. Receive Payload Data Output Interface Timing............................................................................................. 33

Figure 14. Receive Payload Data Output Interface Timing (Nibble Mode Operation) .................................................... 33

Figure 15. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ........................................... 34

Figure 16. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) ..................................... 34

Figure 17. Microprocessor Interface Timing - Intel-type Programmed I/O Read Operation ........................................... 35

Figure 18. Microprocessor Interface Timing - Intel-type Programmed I/O Write Operation............................................ 35

Figure 19. Microprocessor Interface Timing - Motorola-type Programmed I/O Read Operation .................................... 36

Figure 20. Microprocessor Interface Timing - Motorola-type Programmed I/O Write Operation .................................... 36

Figure 21. Microprocessor Interface Timing - Reset Pulse Width................................................................................... 36

2.0 The Microprocessor Interface Block ................................................................................................ 37

Figure 22. Block Diagram of the Microprocessor Interface Block ................................................................................... 37

2.1 T

ICROPROCESSOR

NTERFACE

LOCK

IGNASL

.......................................................................................... 37

ABLE

1: D

ESCRIPTION OF

ICROPROCESSOR

NTERFACE

IGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE

NTEL AND

OTOROLA

ODES

........................................................................................................................................... 38

ABLE

2: D

ESCRIPTION OF

ICROPROCESSOR

NTERFACE

IGNALS

OPERATING IN THE

NTEL

ODE

................................. 38

ABLE

3: D

ESCRIPTION OF THE

ICROPROCESSOR

NTERFACE

IGNALS

OPERATING IN THE

OTOROLA

ODE

.................. 39

2.2 I

NTERFACING THE

XRT72L52 DS3/E3 F

RAMER TO THE

OCAL

µC/µP

VIA THE

ICROPROCESSOR

NTERFACE

LOCK

2.2.1 Interfacing the XRT72L52 DS3/E3 Framer to the Microprocessor over an 8 bit wide bi-directional Data Bus

2.2.2 Data Access Modes ............................................................................................................................... 40

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Microprocessor Interface Timing - Intel-type Programmed I/O Read Operation ........................................... 41

Microprocessor Interface Timing - Intel-type Programmed I/O Write Operation............................................ 42

Microprocessor Interface Timing - Motorola-type Programmed I/O Read Operation .................................... 43

Microprocessor Interface Timing - Motorola-type Programmed I/O Write Operation .................................... 44

2.3 O

-C

HIP

EGISTER

RGANIZATION

................................................................................................................... 44

2.3.1 Framer Register Addressing .................................................................................................................. 44

ABLE

4: R

EGISTER

DDRESSING OF THE

RAMER

ROGRAMMER

EGISTERS

.................................................................... 44

2.3.2 Framer Register Description .................................................................................................................. 48

ART

UMBER

EGISTER

DDRESS

= 0

02) ............................................................................................ 51

ERSION

UMBER

EGISTER

DDRESS

= 0

03)....................................................................................... 52

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Description	TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER	TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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