•
CD4017B, CD4022B
Typel
COS/MOS Counter/Dividers
High-Voltage Types (20-Volt Rating)
CD4017B-Decade Counter with
10 Decoded Outputs
CD4022B-Octal Counter with
8 Decoded Outputs
The RCA-CD4017B and CD4022B are 5-
stage and 4-stage Johnson counters having
10 and 8 decoded outputs, respectively.
Inputs Include a CLOCK, a RESET, and a
CLOCK INHIBIT signal. Schmitt trigger
action In the CLOCK Input circuit provides
pulse shaping that allows unlimited clock
Input pulse rISe and fall times.
These counters are advanced one count at
the positive clock signal tranSition If the
CLOCK INHIBIT signal IS low. Counter
advancement via the clock line is inhibited
when the CLOCK INHIBIT signal IS high.
A high RESET signal clears the counter to
ItS zero count. Use of the Johnson counter
configuration permits high-speed operation,
2-lnput decode-gating and spike-free de-
coded outputs Anti-lock gating IS prOVided,
thus assuring proper counting sequence The
decoded outputs are normally low and go
high only at their respective decoded time
slot. Each decoded output remains high for
one full clock cycle. A CARRY-OUT Signal
completes one cycle every 10 clock Input
cycles In the CD4017B or every 8 clock
Input cycles
10
the CD4022B and IS used to
"0"
Features:
• Fully static operation
• Medium-speed operation _ ..
10 MHz (typ.) at VDD = 10 V
• Standardized, symmetrical output
characteristics
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
CLOCK
CLOCK
INHIBIT
14
"I"
"2"
13
"3"
10 "4"
RESET I '
","
"6"
"7 "
"e"
II
"9"
'2
CARRY
OUT
App/ications:
• Decade counter/decimal decode display
(CD4017B)
• Binary counter/decoder
• Frequency division
• Counter control/timers
• Divide-by-N counting
• For further application information,
see ICAN-G1GG "COS/MOS MSI
Counter and Register Design and
Applications"
npple-clock the succeeding device in a multl-
device counting chain
The CD40178 and CD40228-series types are
supplied in 16-lead -hermetic dual-in-line
ceramic packages (D and F suffixes), 16-
lead dual-in-line plastiC package (E suffiX).
16-lead ceramic flat packages (K suffix), and
in chip form (H suffiX).
CD4017B
'2C'-2~O".2
Functional Diagram
CLOCK
CLOCK
INHIBIT
RESET
14
"0"
13
15
"6"
10
12
CARRY
OUT
"7"
CD4022B
Functional Diagram
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges:
CHARACTERISTICS
Supply-Voltage Range (For T A = Full Package-
Temperature Range)
Clock Input Frequency, fCl
5
10
15
5
10
1G
5
10
15
5
10
15
5
10
15
5
10
15
VDD
(V)
lIMITS
Min.
3
Max.
18
2_5
5
5.5
V
UNITS
3
VSS
I.
16
15
14
13
12
II
Voo
RESET
CLOCK
CLOCK INHIBIT
CARRY OUT
9
10
9
92CS_244'9RI
-
-
-
200
90
60
TOP VIEW
MHz
CD4017B
TERMINAL DIAGRAM
-
Clock Pulse Width, tw
-
-
ns
I.
Clock Rise
&
Fall Time, trCL' tfCL
UNLIMITED
6
NC
2
3
16
15
14
13
12
II
Voo
RESET
CLOCK
CLOCK INHIBIT
CARRY OUT
Clock Inhibit Setup Time, ts
230
100
70
260
110
60
400
280
150
Reset Pulse Width, tRW
Reset Removal Time, t rem
-
-
-
-
-
-
-
-
3
VSS
ns
10
9
NC
92CS-24464RI
ns
TOP VIEW
NC -
no connection
CD4022B
TERMINAL DIAGRAM
ns
-
100 __________________________________________________________________
II
CD4017B, CD4022B Typ
s
o
CARRY OUT
(,lOC~
CLOCK INHIBIT
\~------------------------------
________
D
ISl
~f)I~
______________________
~
__________
D
C5!
D
~r;\~
______________________
lf4J
____________
-Jf\\~
____________________
_________________
______________
-Jf6\~
----------------~f1i~
_______________
VDD
•
~,
CARRY OUT
-----------------------~~~=======
Fig,
2":'
Tlmmg diagram for CD40178,
------------------~~~------------
" " " ' " " " ". . f i
COSIMOS
PRUTECTIDN NUWORK
d
q
VSS
92Cl- 28745A2
CARRY OUT
ClOCK
f~~'~~T
"0"
______________________
~r___i~
______________
"'""'O'I"-____________......
fO'l...________________......
f"O'L
~
m
'2'
~
r---n'---____________
_J~~
II
"3"
"4"
--I3'
________
~~I...
(311...___________
________________
_ _ _ _ _ _ _ __
f5\~
D
Q2
D
03
"5"
__________
...Jm
_______
'0'
"7"
C~~~1
_ _ _ _ _ _ _ _
~f6\
~
_ _ _ _ _ _ _ _ _ _
--'ml..._________________
~
- - - - - - - - \ . ._ _ _ _ _
~--------\
______
.__Jr_
Fig,
4 -
Timing diagram for CD40228
• ALL INPUTS PROTECTED BY
COS/MOS PF:oTECTION NETWORK
s
vss
,
92Cl-28748A2
Fig.
3 -
Logic diagram for CD40228,
______________________________________________________________________ 101
CD4017B, CD4022B Typ
s
MAXIMUM RATINGS,
Absolute·Maximum Values.
DC SUPPL Y·VOL TAGE RANGE. (VOOI
(Voltages referenced to VSS Terminal)
-05to+20V
INPUT VOLTAGE RANGE. ALL INPUTS
-0 5 to V DO +05 V
DC INPUT CURRENT. ANY ONE INPUT
±10mA
POWER DISSIPATION PoER PACKAGE (PO'
For T A
=
-40 to +60 C (PACKAGE TYPE EI
500mW
0
Derate Linearly at 12 mW;oC to 200 mW
For T A
=
+60 to +85
~
(PACKAGE TYPE EI
For T A
=
-55 to +100 C (PACKAGE TYPES O. F)
°
500mW
For TA
=
+100 to +125°C (PACKAGE TYPES D. FI
Derate Linearly at 12 mWI C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A
=
FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl
100mW
OPERATlNG·TEMPERATURE RANGE (TA'
PACKAGE TYPES D. F. H
PACKAGE TYPE E
STORAGE TEMPERATURE RANGE (T
st
I
LEAD TEMPERATURE (DURING
SOLO~RING)
At distance
1/16
±
1/32 Inch (1.59
±
079 mm) from case for 10 s max
-55 to + 125:C
-40to+85 C
0
-65 to +150 C
OUIN-TO-SOUIICE IIOI..TAGE tVOSI-V
Fig.
5-
Typical output low (sink) current
charac teristics.
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (oC)
CHARAC-
CONDITIONS
Values
at
-55, +26, +126
Apply
to
D,F,H Paclulges
TERISTIC
Value.
at
-10,
+25, +85
Apply
to
E Package
+26
Vo
VIN VDO
IV)
IV) IV)
-55
-10
+85 +125
Min. Typ.
Max.
Quiescent
Device
Current,
100 Max.
u
N
I
T
S
DRAIN-TO-SOURCE IIOI..TAG£ CVoSI-V
-
-
0,5
0,10
0,15
0,20
0,5
0,10
0,15
0,5
0,5
0,10
0,15
0,5
0,10
0,15
0,5
0,10
0,15
5
10
15
20
5
10
15
5
10
20
100
0.64
1.6
4.2
5
10
20
100
0.61
1.5
4
150
300
600
3000
0.42
1.1
150
300
600
3000
0.36
0.9
2.4
-
-
-
-
0.51
1.3
3.4
0.04
0.04
0.U4
0.08
1
2.6
6.8
-1
-3.2
-2.6
-6.8
-
-
0.4
0.5
15
46
2.5
9.5
135
5
10
p.A
20
100
Fig.
6-
Minimum output low (sink) current
characteristics.
OllAIN-TO'SOURCE VOLTAGE 'VOSI-V
,'e't.'.'_'
Output Low
(Sink) Current
IOL Min.
Output High
(Source)
Current,
IOH Min
Output Vo'ldge
Low·Le,,·I.
VOL Max
Output
Voltage
Hlgh·Leve
l
VOH Mill
Input Low
Voltage
VIL Max.
Input High
Voltage,
VIHMin.
Input Current
liN Max.
2.8
5 -0.64 -0.61
-2 -1.8
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
18
±0.1
±0.1
-1.6
-4.2
-1.5
-4
-0.42 -0.36 -0.51
-1.3 -1.15 -16
-1.1
-28
-0.9
-2.4
-1.3
-3.4
-
-
-
-
-
mJ!
-
-
Fig.
7-
Typical output high (sourca) currant
characteristics.
OllAIN-TO-SOUIICE IIOI..TAG[ CVoSI-Y
-
-
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3
4
3.5
7
-
-
0 0.05
0 0.05
0 0.05
V
5
10
15
-
-
..
-
4.95
9.95
14.95
-
-
-
1.5
3
-
05,4.5
1,9
1.5,13.5
0.5,4.5
1,9
1.5,13.5
-
-
-
-
-
-
3.5
7
-
-
-
-
-
-
-
4
V
-
0,18
11
±1
±1
11
-
-
-
-
Fig.
8-
Minimum output high (source) current
characteristics.
-
-
±10- 5 ±0.1
p.A
AI
WI
102 ______________________________________________________________________
CD4017B, CD4022B Types
DYNAMIC ELECTRICAL CHARACTERISTICS
At T A = 25°C. Input t r •
tt
= 20 ns. CL = 50 pF. RL = 200 kSl
CHARACTERISTIC
CONDITIONS
VDD(V)
LIMITS
Min. Typ. Max.
UNITS
CLOCKED OPERATION
Propagation Delay Time. tpHL' tpLH
Decode Out
Carry Out
E.
10
1E,
E,
-
-
-
-
325
135
85
300
125
80
100
50
40
5
10
11
100
45
30
650
270
170
600
250
160
200
100
80
ns
10
15
E,
1G
Hi
E,
1C
15
5
-
-
lOAD CAPACITANCE eCL'-pF
Transition Time, tTHL' tTLH
Carry Out or Decode Out Line
-
-
Fig. 10- Typical transition time as a function
of load capacitance.
ns
-
2.5
5
5.5
Maximum Clock Input Frequency. fCL.
-
-
-
200
90
60
MHz
-
-
-
MInimum Clock Pulse Width, tw
Clock Rise or Fall Time, trCL. tfCL
i
10
15,
5,10,15
5
10
15
Any Input
ns
5
300
~
ii
~
200
100
UNLIMITED
!
ns
f
Minimum Clock Inhibit
to Clock Setup Time. ts
Input Capacitance, CIN
RESET OPERATION
Propagation Delay Time, tpHL' tpLH
Carry Out or Decode Out Lines
-
-
-
-
-
115
50
35
5
230
100
70
30
40
00
70
eo
90
100
lOAD CAPACITANCE eC L I -
pF 92CS',094'
-
530
230
170
pF
Fig.
11 -
Typical propagation delay time as a
function of load capacitance (clock
to
decode output).
5
10
15
5
10
15
5
10
15
-
-
-
-
265
115
85
ns
Minimum Reset Pulse Width, tw
Minimum Reset Removal Time
• Measured with respect to carry output lone
-
-
-
-
130 260
55 110
30
60
200 400
140 280
75 150
ns
~
ns
i
i
~
z
300
200
100
20
30
40
00
60
70
90
100
BO
lOAD CAPACITANCE eCl 1 - pF 92CS"0946
---I
~IS
CLOCK~~
F,g.
12 -
TypIcal propagatIon delay tIme as a
functIon of load capacItance (clock
to carry·out).
10
AMBIENT TEMPERATURE
~~~~ ~~-----------------------------------------
RESET ____-'-__________________
~
--' .. -tpRHl
\~----~
--I
r--tPHL
1I~
DECOOEC1>~~:
------'\I
OUTPUT
_____________
____1fl
I
PRLH
92CS' 30948
10
i
DELAYS MEASURED BETWEEN
~
%
LEVEI.S ON ALL WAVEFORMS
.II.
III
10
INPUT
CLOCK
FREO
e
'cl,-kH.
Fig.
9-
Propagation delay, setup, and
hold tIme waveforms
FIg.
13 -
Typical dyanamlc power diSSIpatIon as a
. function of clock Input frequency.
____________________________•___________________________________________ 103
CD40178, CD40228 Types
INPUT5.
o
Vss
Voo
INPOU'
'00
""
~
Vss
~:~~~::,~~':.';~S
TO BOTH VOD AND Vss
CONNECT ALL UNUSED
INPlITS
TO
EITHER
VDD
OR
Vss
Vss
9ZCS-2144'R'
Vss
F,g.
14 -
Ouiescent-device-
current test circUIt
FIg.
15 -
Input-leakage current.
Fig_
16 -
Input-voltage test circuit.
.-=-:..;.;....:..;.;:...+-~c..;;.;..--+
...
FOR
ALTERNATE CDUT
N - 2 TO 10
I-CLOCK -
N
L _ _ _ _ _ _ _ _ _ _ _ _
-.J
I
92C5-30949
!l2CS-S0950
FIg.
17 -
DynamIC power diSSIpatIon test cIrcuit.
FIg.
18 -
DIVIde by Ncounter (N
~
70) with N
decoded outputs.
When the Nth decoded output IS reached
(Nth clock pulse) the S-R flip flop (con-
structed from two NOR gates of the
CD4001 B) generates a reset pulse which
clears the CD4017B or CD4022B to its zero
count. At this tIme, If the Nth decoded out-
put is greater than or equal to 6 in the CD-
4017B or 5 in the CD4022B, the COUT line
goes high to clock the next CD4017B or CD-
4022B counter section. The "0" decoded
output also goes high at this time. Cornci-
dence of the clock low and decoded "0"
output low resets the S-R flip flop to enable
the CD4017B or CD4022B. If the Nth de-
coded output is less than 6 (CD4017B) or 5
(CD4022BI. the COUT line will not go high
and, therefore, cannot be used. In this case
"0" decoded output may be used to perform
the clocking function for the next counter.
l~
(2
(2.210- 24131
g2eN-109"
92CM-30952
CD4017BH
CD4022BH
The photographs and dImensIons of each
COS/MOS
chIp represent a chIp when It IS part of the wafer.
When the w-:,fer IS cut Into chips, the cleavage
o
angles are
57
Instead of 90 wIth respect to the
face of the chIp Therefore, the Isolated chIp IS
actually
7
mtls (0
17
mmJ larger m both d,mens,ons.
DimenSions In parentheses are In mtll,meters and
are deflved Irom the baSIC mch dimenSIons as m·
d,cated Gfld graduations are In mtls
(10-
3
Inch)
104 ______________________________________________________________________
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