EP1S60B956I6 datasheet, PDF - EEWORLD Datasheet

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EP1S60B956I6: DescriptionField Programmable Gate Array, 57120-Cell, CMOS, PBGA956, 40 X 40 MM, 1.27 MM PITCH, BGA-956; CategoryProgrammable logic devices Programmable logic; File Size1020KB，196 Pages; ManufacturerAltera (Intel)

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EP1S60B956I6 Overview

Field Programmable Gate Array, 57120-Cell, CMOS, PBGA956, 40 X 40 MM, 1.27 MM PITCH, BGA-956

EP1S60B956I6 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA, BGA956,31X31,50
Contacts	956
Reach Compliance Code	compli
JESD-30 code	S-PBGA-B956
JESD-609 code	e0
Number of entries	1022
Number of logical units	57120
Output times	1022
Number of terminals	956
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA956,31X31,50
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5,1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
Base Number Matches	1

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Stratix

Programmable Logic

Device Family

Data Sheet

April 2002, ver. 2.0

Introduction

Preliminary

Information

The Stratix family of programmable logic devices (PLDs) is based on a

1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to

114,140 logic elements (LEs) and up to 10 Mbits of RAM. Stratix devices

offer up to 28 digital signal processing (DSP) blocks with up to

224 (9-bit

9-bit) embedded multipliers, optimized for DSP applications

that enable efficient implementation of high-performance filters and

multipliers. Stratix devices support various I/O standards and also offer

a complete clock management solution with its hierarchical clock

structure with up to 420-MHz performance and up to 12 phase-locked

loops (PLLs).

■

Features...

■

Altera Corporation

DS-STXFAMLY-2.0

10,570 to 114,140 LEs; see

Table 1

Up to 10,118,016 RAM bits (1,264,752 bytes) available without

reducing logic resources

TriMatrix

memory consisting of three RAM block sizes to

implement true dual-port memory and first-in first-out (FIFO)

buffers up to 312 MHz

High-speed DSP blocks provide dedicated implementation of

multipliers (at up to 250 MHz), multiply- accumulate functions, and

finite impulse response (FIR) filters

Up to 16 global clocks with 22 clocking resources per device region

Up to 12 enhanced PLLs per device provide spread spectrum,

programmable bandwidth, clock switch-over, real-time PLL

reconfiguration, and advanced multiplication and phase shifting

Support for numerous single-ended and differential I/O standards

High-speed differential I/O support on up to 116 channels with up to

80 channels optimized for 840 megabits per second (Mbps)

Support for high-speed networking and communications bus

standards including RapidIO, UTOPIA IV, CSIX, HyperTransport

technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and

SFI-4

Terminator

technology provides on-chip termination for

differential and single-ended I/O pins with impedance matching

Support for high-speed external memory, including zero bus

turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM,

double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and

single data rate (SDR) SDRAM

Support for multiple intellectual property megafunctions from Altera

MegaCore

functions and Altera Megafunction Partners Program

(AMPP

) megafunctions

Support for remote configuration updates

Stratix Programmable Logic Device Family Data Sheet

Preliminary Information

Table of

Contents

Introduction ........................................................................................................1

Features ...............................................................................................................1

Table of Contents ...............................................................................................4

Functional Description ......................................................................................5

Logic Array Blocks.............................................................................................7

Logic Elements .................................................................................................10

MultiTrack Interconnect .................................................................................18

TriMatrix Memory ...........................................................................................26

Digital Signal Processing Block......................................................................54

PLLs & Clock Networks..................................................................................76

I/O Structure ..................................................................................................105

High-Speed Differential I/O Support.........................................................128

Power Sequencing & Hot Socketing ...........................................................133

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support.....................................133

SignalTap Embedded Logic Analyzer ........................................................138

Configuration .................................................................................................138

Temperature Sensing Diode.........................................................................144

Operating Conditions....................................................................................146

Power Consumption......................................................................................157

Timing Model .................................................................................................158

Software...........................................................................................................195

Device Pin-Outs..............................................................................................195

Ordering Information....................................................................................195

Altera Corporation

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