Features
•
Incorporates the ARM7TDMI
®
ARM
®
Thumb
®
Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE
™
(In-circuit Emulation)
256K Bytes of On-chip SRAM
– 32-bit Data Bus, Single-clock Cycle Access
1024K Words 16-bit Flash Memory (2M bytes)
– Single Voltage Read/Write,
– Sector Erase Architecture
– Erase Suspend Capability
– Low-power Operation
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
– Reset Input for Device Initialization
– Sector Program Unlock Command
– 128-bit Protection Register
– Factory-programmed AT91 Flash Memory Uploader Software
Fully Programmable External Bus Interface (EBI)
– Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes
– Software Programmable 8/16-bit External Data Bus
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
32 Programmable I/O Lines
3-channel 16-bit Timer/Counter
– 3 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
2 USARTs
– Two Dedicated Peripheral Data Controller (PDC) Channels per USART
Programmable Watchdog Timer
Advanced Power-saving Features
– CPU and Peripherals Can be De-activated Individually
Fully Static Operation:
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85° C
2.7V to 3.6V I/O Operating Range, 1.65V to 1.95V Core Operating Range
-40° C to 85° C Temperature Range
Available in a 121-ball 10 x 10 x 1.26 mm BGA Package with 0.8 mm Ball Pitch
•
•
AT91 ARM
Thumb-based
Microcontrollers
AT91FR40162SB
Preliminary
Summary
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•
•
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•
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•
•
•
NOTE:
This is a summary document.
The complete document is available on
the Atmel website at
www.atmel.com.
6410BS–ATARM–12-Jan-10
1. Description
The AT91FR40162SB is a member of the Atmel AT91 16/32-bit Microcontroller family, which is
based on the ARM7TDMI processor core. The processor has a high-performance 32-bit RISC
architecture with a high-density 16-bit instruction set and very low power consumption.
The AT91FR40162SB ARM microcontroller features 2 Mbits of on-chip SRAM and 2 Mbytes of
Flash memory in a single compact 121-ball BGA package. Its high level of integration and very
small footprint make the device ideal for space-constrained applications. The high-speed on-
chip SRAM enables a performance of up to 74 MIPs in typical conditions with significant power
reduction and EMC improvement over an external SRAM implementation.
The Flash memory may be programmed via the JTAG/ICE interface or the factory-programmed
Flash Memory Uploader (FMU) using a single device supply, making the AT91FR40162SB suit-
able for in-system programmable applications.
2. Migrating from the AT91FR40162S to the AT91FR40162SB
2.1
Hardware Requirements
The AT91FR40162SB is pin-to-pin compatible to the AT91FR40162S, so the AT91FR40162SB
can be soldered in place of the AT91FR40162S without any other hardware changes.
The AT91FR40162SB does not feature a VPP pin, thus ball D5 of the 121-ball BGA package of
the AT91FR40162SB is NC (Not connected). This ball can either be connected to a supply up to
13V (as could be the VPP ball of the AT91FR40162S), grounded or left unconnected.
2.2
Software Requirements
Except for the Flash memory, the processor, the architecture and the peripherals of both the
AT91FR40162S and the AT91FR40162SB are identical, any program written for an
AT91FR40162S-based system can run as is on the same system built with an
AT91FR40162SB, with the exception of aspects related to the Flash memory.
2.3
Flash Memory Difference
Som e features of the embedded Flash memories in the AT91FR40162S and the
AT91FR40162SB are not fully identical.
2.3.1
Device ID
The Device Code of the Flash Memory of the AT91FR40162SB is 01C0H instead of 00C0H for
the AT91FR40162S. Users who this Device Code must modify the software.
2.3.2
VPP Features
As the AT91FR40162SB does not feature a VPP pin, neither the write protection feature nor the
double-word fast write feature are available on this device.
If the hardware write protection feature is used on the AT91FR40162S, it should be replaced by
a software-controlled write protection method with the Sector Lockdown command, or removed
from the application.
If the Double Byte/Word Program command was used on the AT91FR40162S, the user needs to
change the flash programming sequence and to use only the standard Byte/Word Program
command.
2
AT91FR40162SB
6410BS–ATARM–12-Jan-10
AT91FR40162SB
The VPP Status I/O3 does not exist anymore in the Status word returned by the Flash Memory.
2.3.3
Erase Cycle Timings
The 32K Word sector erase cycle time maximum value has been increased from 5 seconds to
6 seconds. In case the end of erase cycle is not used, but a fixed timeout is used instead, the
value of the timeout must be checked against the new value.
CFI Common Flash Interface
The Common Flash Interface table (Table
12-5, “Common Flash Interface Definition,” on
page 68)
Erase block information of the 64-KByte and the 8-KByte sectors addresses was not
fully CFI-compliant on the AT91FR40162S. The AT91FR40162SB is fully CFI-compliant, and
thus the Erase block information of the 64-KByte and the 8-KByte sector addresses in the Com-
mon Flash Interface table have changed.
Users who managed the programming of the flash with the CFI algorithm on the AT91FR40162S
should adapt their programming for the AT91FR40162SB.
2.3.5
Fully Green Package
The AT91FR40162S is RoHS compliant, whereas the AT91FR40162SB is fully Green qualified.
This has no impact on the soldering profile to be used, but only improves environmental
considerations.
2.3.4
3
6410BS–ATARM–12-Jan-10
3. Pin Configuration
Figure 3-1.
AT91FR40162SB Pinout for 121-ball BGA Package (Top View)
A1 Corner
1
2
3
4
5
6
7
8
9
10
11
A
P21/TXD1
NTRI
P22
RXD1
P19
P16
P15
RXD0
GND
P11
P8
VDDCORE
IRQ2
TIOB2
P10
IRQ1
P9
IRQ0
P7
TIOA2
P3
TCLK1
P6
TCLK2
P4
TIOA1
GND
P2
TIOB0
B
P20
SCK1
P18
P17
P12
FIQ
NBUSY
VDDIO
GND
P1
TIOA0
C
VDDIO
GND
NUB
NWR1
P14
TXD0
P13
SCK0
P5
TIOB1
A16
D15
P0
TCLK0
D
P23
MCKI
NRST
NC
(1)
NRSTF
A14
A15
D12
D14
VDDIO
E
P24
BMS
P25
NWDOVF
MCK0
A3
A8
D11
D10
D13
NC
NC
D3
F
GND
TMS
GND
TCK
NOE
NRD
D9
A11
D7
D8
NC
NC
G
TDO
NWE
NWR0
A2
TDI
NCS0
D2
D5
D4
D6
GND
NC
H
P26
VDDCORE VDDIO
NCS2
NC
NCSF
NC
D0
D1
P31/A23
CS4
NC
NC
J
NWAIT
GND
P27
NCS3
A5
NC
VDDIO
GND
GND
A19
P30/A22
VDDIO
CS5
K
P29/A21
VDDCORE
CS6
NCS1
NLB
A0
GND
A7
VDDIO
A10
A13
GND
A17
L
GND
A1
A4
A6
VDDIO
A9
A12
GND
VDDIO
A18
A20
Note:
1. Not connected, can either be connected to GND, VCC or left unconnected.
4
AT91FR40162SB
6410BS–ATARM–12-Jan-10
AT91FR40162SB
4. Signal Description
Table 4-1.
Module
AT91FR40162SB Signal Description
Name
A0 - A23
D0 - D15
NCS0 - NCS3
CS4 - CS7
NWR0
NWR1
Function
Address Bus
Data Bus
External Chip Select
External Chip Select
Lower Byte 0 Write Signal
Upper Byte 1 Write Signal
Read Signal
Write Enable
Output Enable
Upper Byte Select
Lower Byte Select
Wait Input
Boot Mode Select
Fast Interrupt Request
External Interrupt Request
Timer External Clock
Multi-purpose Timer I/O Pin A
Multi-purpose Timer I/O Pin B
External Serial Clock
Transmit Data Output
Receive Data Input
Parallel IO Line
Watchdog Overflow
Master Clock Input
Master Clock Output
Hardware Reset Input
Tri-state Mode Select
Test Mode Select
Test Data Input
Test Data Output
Test Clock
Type
Output
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
I/O
I/O
I/O
Output
Input
I/O
Output
Input
Output
Input
Input
Input
Input
Output
Input
Active
Level
–
–
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
–
–
–
–
–
–
–
–
–
–
Low
–
–
Low
Low
–
–
–
–
Schmidt trigger, internal pull-up
Schmidt trigger
Sampled during reset
Schmidt trigger, internal pull-up
Schmidt trigger, internal pull-up
Open drain
Schmidt trigger
Sampled during reset; must be driven low
during reset for Flash to be used as boot
memory
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
Used to select external devices
A23 - A20 after reset
Used in Byte Write option
Used in Byte Write option
Used in Byte Write option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Comments
Valid after reset; do not reprogram A20 to
I/O, as it is MSB of Flash address
EBI
NRD
NWE
NOE
NUB
NLB
NWAIT
BMS
FIQ
AIC
IRQ0 - IRQ2
TCLK0 - TCLK2
Timer
TIOA0 - TIOA2
TIOB0 - TIOB2
SCK0 - SCK1
USART
TXD0 - TXD1
RXD0 - RXD1
PIO
WD
Clock
MCKO
NRST
Reset
NTRI
TMS
TDI
ICE
TDO
TCK
P0 - P31
NWDOVF
MCKI
5
6410BS–ATARM–12-Jan-10
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