FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11404-2E
MEMORY Mobile FCRAM
TM
CMOS
16 Mbit (1 M word
×
16 bit)
Mobile Phone Application Specific Memory
MB82D01171A
-80/80L/80LL/85/85L/85LL/90/90L/90LL
CMOS 1,048,576-WORD
×
16 BIT
Fast Cycle Random Access Memory
with Low Power SRAM Interface
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DESCRIPTION
The Fujitsu MB82D01171A is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static
Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. This
MB82D01171A is suited for low power applications such as Cellular Handset and PDA.
Note: FCRAM is a trademark of Fujitsu Limited, Japan.
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PRODUCT LINEUP
Parameter
Access Time (t
AA
Max, t
CE
Max)
Active Current (I
DDA1
Max)
Standby Current (I
DDS1
Max)
Power Down Current (I
DDP
Max)
MB82D01171A
80
80L
80 ns
80LL
85
85L
85 ns
20 mA
200
µA
100
µA
70
µA
200
µA
100
µA
70
µA
200
µA
100
µA
70
µA
10
µA
85LL
90
90L
90 ns
90LL
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PACKAGES
48-ball plastic FBGA
48-ball plastic FBGA
(BGA-48P-M16)
(BGA-48P-M18)
MB82D01171A
-80/80L/80LL/85/85L/85LL/90/90L/90LL
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FEATURES
•
•
•
•
•
•
Asynchronous SRAM Interface
1 M word
×
16 bit Organization
Fast Random Cycle Time : t
RC
=
90 ns
Fast Random Access Time : t
AA
=
t
CE
=
80 ns, 85 ns, 90 ns
Low Power Consumption : I
DDS1
=
200
µA,
100
µA
(L version) , 70
µA
(LL version)
Wide Operating Conditions : V
DD
= +2.3
V to
+2.7
V
+2.7
V to
+3.1
V
+3.1
V to
+3.5
V
T
A
= −30 °C
to
+85 °C
• Byte Write Control
• 4 words Address Access Capability
• Power Down Control by CE2
2
MB82D01171A
-80/80L/80LL/85/85L/85LL/90/90L/90LL
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PIN ASSIGNMENTS
(TOP VIEW)
Flash Compatible FBGA
(suffix PBT)
1
2
3
4
5
6
1
SRAM Compatible FBGA
(suffix PBN)
2
3
4
5
6
A
B
C
D
E
F
G
H
A
4
A
3
A
2
A
1
A
0
CE1
OE
V
SS
A
17
A
7
A
6
A
5
DQ
1
DQ
9
UB
LB
A
18
NC
DQ
3
CE2
WE
NC
A
19
DQ
6
A
8
A
9
A
10
A
11
DQ
8
A
12
A
13
A
14
A
15
A
16
NC
A
B
C
D
E
F
G
H
LB
DQ
9
OE
UB
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
A
2
CE1
DQ
2
DQ
4
DQ
5
DQ
6
WE
A
11
CE2
DQ
1
DQ
3
V
DD
V
SS
DQ
7
DQ
8
NC
DQ
10
DQ
11
V
SS
V
DD
DQ
12
DQ
13
DQ
11
DQ
13
DQ
15
V
DD
DQ
5
DQ
15
DQ
14
DQ
16
A
18
A
19
A
8
DQ
10
DQ
12
DQ
2
DQ
4
DQ
14
DQ
16
DQ
7
V
SS
(BGA-48P-M16)
(BGA-48P-M18)
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PIN DESCRIPTION
Pin Name
A
0
to A
19
CE1
CE2
WE
OE
LB
UB
DQ
1
to DQ
8
DQ
9
to DQ
16
V
DD
V
SS
NC
Address Input
Chip Enable (Low Active)
Chip Enable (High Active)
Write Enable (Low Active)
Output Enable (Low Active)
Lower Byte Write Control (Low Active)
Upper Byte Write Control (Low Active)
Lower Byte Data Input/Output
Upper Byte Data Input/Output
Power Supply
Ground
No Connection
Description
3
MB82D01171A
-80/80L/80LL/85/85L/85LL/90/90L/90LL
s
BLOCK DIAGRAM
V
DD
V
SS
A
0
to A
19
Address
Latch &
Buffer
Row
Decoder
Memory
Cell
Array
16,777,216 bit
DQ
1
to DQ
8
I/O
Buffer
DQ
9
to DQ
16
Input Data
Latch &
Control
Sense /
Switch
Output
Data
Control
Column /
Decoder
Address
Latch &
Buffer
CE2
Power
Control
Timing
Control
CE1
WE
LB
UB
OE
4
MB82D01171A
-80/80L/80LL/85/85L/85LL/90/90L/90LL
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FUNCTION TRUTH TABLE *
1
Mode
Power Down *
2
Standby (Deselect)
Output Disable*
3
Read*
4
Write
Write (Lower Byte)
Write (Upper Byte)
H
L
H
H
CE1
X
H
CE2
L
WE
X
X
OE
X
X
H
L
LB
X
X
X
X
L
L
H
UB
X
X
X
X
L
H
L
DQ
1
to
DQ
8
High-Z
High-Z
High-Z
Output
Valid
Input
Valid
Input
Valid
Invalid
DQ
9
to
DQ
16
High-Z
High-Z
High-Z
Output
Valid
Input
Valid
Invalid
Input
Valid
I
DDA
Yes
I
DD
I
DDP
I
DDS
Data
Retention
No
L
*1 : V
=
Valid, L
=
Logic Low, H
=
Logic High, X
=
either “L” or “H”, High-Z
=
High Impedance
*2 : Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
*3 : Output Disable mode should not be kept longer than 1
µs.
*4 : Byte control at Read mode is not supported.
5
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