D5C031-40 datasheet, PDF - EEWORLD Datasheet

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D5C031-40: Description300 gate CMOS pld; CategoryProgrammable logic devices Programmable logic; File Size353KB，12 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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D5C031-40 Overview

300 gate CMOS pld

D5C031-40 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	DIP
package instruction	WDIP, DIP20,.3
Contacts	20
Reach Compliance Code	compli
Other features	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE
maximum clock frequency	18.5 MHz
JESD-30 code	R-GDIP-T20
JESD-609 code	e0
length	24.825 mm
Dedicated input times	8
Number of I/O lines	8
Number of entries	18
Output times	8
Number of product terms	74
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	WDIP
Encapsulate equivalent code	DIP20,.3
Package shape	RECTANGULAR
Package form	IN-LINE, WINDOW
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	UV PLD
propagation delay	40 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

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D5C031-40 Related Products

	D5C031-40	D5C031	D5C031-50
Description	300 gate CMOS pld	300 gate CMOS pld	300 gate CMOS pld
Is it Rohs certified?	incompatible	-	incompatible
Maker	Intel	-	Intel
Parts packaging code	DIP	-	DIP
package instruction	WDIP, DIP20,.3	-	WDIP, DIP20,.3
Contacts	20	-	20
Reach Compliance Code	compli	-	compli
Other features	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	-	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE	-	PAL-TYPE
maximum clock frequency	18.5 MHz	-	16.67 MHz
JESD-30 code	R-GDIP-T20	-	R-GDIP-T20
JESD-609 code	e0	-	e0
length	24.825 mm	-	24.825 mm
Dedicated input times	8	-	8
Number of I/O lines	8	-	8
Number of entries	18	-	18
Output times	8	-	8
Number of product terms	74	-	74
Number of terminals	20	-	20
Maximum operating temperature	70 °C	-	70 °C
organize	8 DEDICATED INPUTS, 8 I/O	-	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL	-	MACROCELL
Package body material	CERAMIC, GLASS-SEALED	-	CERAMIC, GLASS-SEALED
encapsulated code	WDIP	-	WDIP
Encapsulate equivalent code	DIP20,.3	-	DIP20,.3
Package shape	RECTANGULAR	-	RECTANGULAR
Package form	IN-LINE, WINDOW	-	IN-LINE, WINDOW
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED
power supply	5 V	-	5 V
Programmable logic type	UV PLD	-	UV PLD
propagation delay	40 ns	-	50 ns
Certification status	Not Qualified	-	Not Qualified
Maximum seat height	5.08 mm	-	5.08 mm
Maximum supply voltage	5.25 V	-	5.25 V
Minimum supply voltage	4.75 V	-	4.75 V
Nominal supply voltage	5 V	-	5 V
surface mount	NO	-	NO
technology	CMOS	-	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	-	THROUGH-HOLE
Terminal pitch	2.54 mm	-	2.54 mm
Terminal location	DUAL	-	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED
width	7.62 mm	-	7.62 mm
Base Number Matches	1	-	1

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