DS1251Y-150 datasheet, PDF - EEWORLD Datasheet

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DS1251Y-150: Description4096K NV SRAM with Phantom Clock; CategoryThe embedded processor and controller Microcontrollers and processors; File Size62KB，12 Pages; ManufacturerDALLAS; Websitehttp://www.dalsemi.com

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DS1251Y-150 Overview

4096K NV SRAM with Phantom Clock

DS1251Y-150 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	DALLAS
package instruction	DIP, DIP32,.6
Reach Compliance Code	unknow
External data bus width	8
Information access methods	PARALLEL, DIRECT ADDRESS
interrupt capability	N
JESD-30 code	R-XDIP-T32
JESD-609 code	e0
Number of terminals	32
Number of timers
On-chip data RAM width	8
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	UNSPECIFIED
encapsulated code	DIP
Encapsulate equivalent code	DIP32,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (number of words)	262144
Maximum slew rate	85 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	MOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
shortest time	1/100 SECOND
Maximum time at peak reflow temperature	NOT SPECIFIED
Volatile	NO
uPs/uCs/peripheral integrated circuit type	TIMER, REAL TIME CLOCK
Base Number Matches	1

DS1251Y-150 Preview

DS1251Y

4096K NV SRAM with Phantom Clock

FEATURES

PIN ASSIGNMENT

A18/RST

A16

A14

A12

DQ0

DQ1

DQ2

GND

A15

A17

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

•

Real time clock keeps track of hundredths of seconds,

minutes, hours, days, date of the month, months, and

years

•

512K x 8 NV SRAM directly replaces volatile static

RAM or EEPROM

•

Embedded lithium energy cell maintains calendar op-

eration and retains RAM data

•

Watch function is transparent to RAM operation

•

Month and year determine the number of days in each

month; valid up to 2100

•

Standard 32–pin JEDEC pinout

•

Full 10% operating range

•

Operating temperature range 0°C to 70°C

•

Accuracy is better than

±1

minute/month @ 25°C

•

Over

10 years of data retention in the absence of

power

32–PIN ENCAPSULATED PACKAGE

740 MIL FLUSH

PIN DESCRIPTION

–A

GND

–DQ

RST

–

Address Inputs

Chip Enable

Ground

Data In/Data Out

Power (+5V)

Write Enable

Output Enable

Reset

•

Available in 120 ns and 150 ns access time

ORDERING INFORMATION

DS1251Y–120

DS1251Y–150

120 ns access

150 ns access

DESCRIPTION

The DS1251Y 4096K NV SRAM with Phantom Clock is

a fully static nonvolatile RAM (organized as 512K words

by 8 bits) with a built–in real time clock. The DS1251Y

has a self–contained lithium energy source and control

circuitry which constantly monitors V

for an out–of–

tolerance condition. When such a condition occurs, the

lithium energy source is automatically switched on and

write protection is unconditionally enabled to prevent

garbled data in both the memory and real time clock.

The Phantom Clock provides timekeeping information

including hundredths of seconds, seconds, minutes,

hours, day, date, month, and year information. The date

at the end of the month is automatically adjusted for

months with less than 31 days, including correction for

leap years. The Phantom Clock operates in either

24–hour or 12–hour format with an AM/PM indicator.

ECopyright

1997 by Dallas Semiconductor Corporation.

patents and other intellectual property rights, please refer to

Dallas Semiconductor data books.

032697 1/12

DS1251Y

RAM READ MODE

The DS1251Y executes a read cycle whenever WE

(Write Enable) is inactive (high) and CE (Chip Enable) is

active (low). The unique address specified by the 17 ad-

dress inputs (A0–A18) defines which of the 512K bytes

of data is to be accessed. Valid data will be available to

the eight data output drivers within t

ACC

(Access Time)

after the last address input signal is stable, providing

that CE and OE (Output Enable) access times and

states are also satisfied. If OE and CE access times are

not satisfied, then data access must be measured from

the later occurring signal (CE or OE) and the limiting pa-

rameter is either t

for CE or t

for OE rather than ad-

dress access.

PHANTOM CLOCK OPERATION

Communication with the Phantom Clock is established

by pattern recognition on a serial bit stream of 64 bits

which must be matched by executing 64 consecutive

write cycles containing the proper data on DQ0. All ac-

cesses which occur prior to recognition of the 64–bit pat-

tern are directed to memory.

After recognition is established, the next 64 read or write

cycles either extract or update data in the Phantom

Clock, and memory access is inhibited.

Data transfer to and from the timekeeping function is ac-

complished with a serial bit stream under control of Chip

Enable (CE), Output Enable (OE), and Write Enable

(WE). Initially, a read cycle to any memory location us-

ing the CE and OE control of the Phantom Clock starts

the pattern recognition sequence by moving a pointer to

the first bit of the 64–bit comparison register. Next, 64

consecutive write cycles are executed using the CE and

WE control of the SmartWatch. These 64 write cycles

are used only to gain access to the Phantom Clock.

Therefore, any address to the memory in the socket is

acceptable. However, the write cycles generated to

gain access to the Phantom Clock are also writing data

to a location in the mated RAM. The preferred way to

manage this requirement is to set aside just one ad-

dress location in RAM as a Phantom Clock scratch pad.

When the first write cycle is executed, it is compared to

bit 0 of the 64–bit comparison register. If a match is

found, the pointer increments to the next location of the

comparison register and awaits the next write cycle. If a

match is not found, the pointer does not advance and all

subsequent write cycles are ignored. If a read cycle oc-

curs at any time during pattern recognition, the present

sequence is aborted and the comparison register point-

er is reset. Pattern recognition continues for a total of 64

write cycles as described above until all the bits in the

comparison register have been matched (this bit pattern

is shown in Figure 1). With a correct match for 64–bits,

the Phantom Clock is enabled and data transfer to or

from the timekeeping registers can proceed. The next

64 cycles will cause the Phantom Clock to either receive

or transmit data on DQ0, depending on the level of the

OE pin or the WE pin. Cycles to other locations outside

the memory block can be interleaved with CE cycles

without interrupting the pattern recognition sequence or

data transfer sequence to the Phantom Clock.

RAM WRITE MODE

The DS1251Y is in the write mode whenever the WE

and CE signals are in the active (low) state after address

inputs are stable. The latter occurring falling edge of CE

or WE will determine the start of the write cycle. The

write cycle is terminated by the earlier rising edge of CE

or WE. All address inputs must be kept valid throughout

the write cycle. WE must return to the high state for a

minimum recovery time (t

) before another cycle can

be initiated. The OE control signal should be kept inac-

tive (high) during write cycles to avoid bus contention.

However, if the output bus has been enabled (CE and

OE active) then WE will disable the outputs in t

ODW

from

its falling edge.

DATA RETENTION MODE

The DS1251Y provides full functional capability for V

greater than 4.5 volts and write protects by approxi-

mately 4.0 volts. Data is maintained in the absence of

without any additional support circuitry. The non-

volatile static RAM constantly monitors V

. Should the

supply voltage decay, the RAM automatically write pro-

tects itself. All inputs to the RAM become “don’t care”

and all outputs are high impedance. As V

falls below

approximately 3.0 volts, the power switching circuit con-

nects the lithium energy source to RAM to retain data.

During power–up, when V

rises above approximately

3.0 volts, the power switching circuit connects external

to the RAM and disconnects the lithium energy

source. Normal RAM operation can resume after V

exceeds 4.5 volts.

032697 2/12

DS1251Y

PHANTOM CLOCK

The Phantom Clock information is contained in eight

registers of 8–bits, each of which is sequentially ac-

cessed one bit at a time after the 64–bit pattern recogni-

tion sequence has been completed. When updating the

Phantom Clock registers, each register must be han-

dled in groups of 8–bits. Writing and reading individual

bits within a register could produce erroneous results.

These read/write registers are defined in Figure 2.

Data contained in the Phantom Clock register is in

binary coded decimal format (BCD). Reading and writ-

ing the registers is always accomplished by stepping

through all eight registers, starting with bit 0 of register 0

and ending with bit 7 of register 7.

PHANTOM CLOCK REGISTER DEFINITION

Figure 1

BYTE 0

HEX

VALUE

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

BYTE 7

NOTE:

The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally dupli-

cated and causing inadvertent entry to the Phantom Clock is less than 1 in 10

. This pattern is sent to the Phantom

Clock LSB to MSB.

032697 3/12

DS1251Y

PHANTOM CLOCK REGISTER DEFINITION

Figure 2

0.1 SEC

0.01 SEC

00–99

RANGE

(BCD)

10 SEC

SECONDS

00–59

10 MIN

MINUTES

00–59

12/24

A/P

HOUR

01–12

00–23

OSC

RST

DAY

01–07

10 DATE

DATE

01–31

MONTH

01–12

10 YEAR

YEAR

00–99

AM-PM/12/24 MODE

Bit 7 of the hours register is defined as the 12– or

24–hour mode select bit. When high, the 12–hour mode

is selected. In the 12–hour mode, bit 5 is the AM/PM bit

with logic high being PM. In the 24–hour mode, bit 5 is

the second 10-hour bit (20–23 hours).

to logic 0, a low input on the RESET pin will cause the

Phantom Clock to abort data transfer without changing

data in the watch registers. Bit 5 controls the oscillator.

When set to logic 1, the oscillator is off. When set to log-

ic 0, the oscillator turns on and the watch becomes op-

erational. These bits are shipped from the factory set to

a logic 1.

OSCILLATOR AND RESET BITS

Bits 4 and 5 of the day register are used to control the

RESET and oscillator functions. Bit 4 controls the

RESET (pin 1). When the RESET bit is set to logic 1, the

RESET input pin is ignored. When the RESET bit is set

ZERO BITS

Registers 1, 2, 3, 4, 5, and 6 contain one or more bits

which will always read logic 0. When writing these loca-

tions, either a logic 1 or 0 is acceptable.

032697 4/12

DS1251Y

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground

Operating Temperature

Storage Temperature

Soldering Temperature

–0.3V to +7.0V

0°C to 70°C

–40°C to +70°C

260°C for 10 seconds (See Note 13)

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

PARAMETER

Power Supply Voltage

Input Logic 1

Input Logic 0

SYMBOL

MIN

4.5

2.2

–0.3

TYP

5.0

MAX

5.5

+0.3

+0.8

UNITS

(0°C to 70°C)

NOTES

DC ELECTRICAL CHARACTERISTICS

PARAMETER

Input Leakage Current

I/O Leakage Current

Output Current @ 2.4 volts

Output Current @ 0.4 volts

Standby Current CE = 2.2 volts

Standby Current CE =

– 0.5 volts

Operating Current t

CYC

= 200 ns

SYMBOL

CCS1

CCS2

CC01

MIN

–1.0

2.0

5.0

3.0

TYP

(0°C to 70°C; V

= 5V

10%)

MAX

+1.0

UNITS

µA

5.0

NOTES

DC TEST CONDITIONS

Outputs are open; all voltages are referenced to ground.

CAPACITANCE

PARAMETER

Input Capacitance

Input/Output Capacitance

SYMBOL

I/O

MIN

TYP

MAX

UNITS

= 25°C)

NOTES

032697 5/12

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DS1251Y-150 Related Products

	DS1251Y-150	DS1251Y	DS1251Y-120
Description	4096K NV SRAM with Phantom Clock	4096K NV SRAM with Phantom Clock	4096K NV SRAM with Phantom Clock
Is it Rohs certified?	incompatible	-	incompatible
Maker	DALLAS	-	DALLAS
package instruction	DIP, DIP32,.6	-	PLASTIC, DIP-32
Reach Compliance Code	unknow	-	unknow
External data bus width	8	-	8
Information access methods	PARALLEL, DIRECT ADDRESS	-	PARALLEL, DIRECT ADDRESS
interrupt capability	N	-	N
JESD-30 code	R-XDIP-T32	-	R-XDIP-T32
JESD-609 code	e0	-	e0
Number of terminals	32	-	32
On-chip data RAM width	8	-	8
Maximum operating temperature	70 °C	-	70 °C
Package body material	UNSPECIFIED	-	UNSPECIFIED
encapsulated code	DIP	-	DIP
Encapsulate equivalent code	DIP32,.6	-	DIP32,.6
Package shape	RECTANGULAR	-	RECTANGULAR
Package form	IN-LINE	-	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED
power supply	5 V	-	5 V
Certification status	Not Qualified	-	Not Qualified
RAM (number of words)	262144	-	262144
Maximum slew rate	85 mA	-	85 mA
Maximum supply voltage	5.5 V	-	5.5 V
Minimum supply voltage	4.5 V	-	4.5 V
Nominal supply voltage	5 V	-	5 V
surface mount	NO	-	NO
technology	MOS	-	MOS
Temperature level	COMMERCIAL	-	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	-	THROUGH-HOLE
Terminal pitch	2.54 mm	-	2.54 mm
Terminal location	DUAL	-	DUAL
shortest time	1/100 SECOND	-	1/100 SECOND
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED
Volatile	NO	-	NO
uPs/uCs/peripheral integrated circuit type	TIMER, REAL TIME CLOCK	-	TIMER, REAL TIME CLOCK
Base Number Matches	1	-	1

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