PRELIMINARY
Am79C987
Hardware Implemented Management Information Base™
(HIMIB™) Device
DISTINCTIVE CHARACTERISTICS
s
Provides repeater management functions,
complying with all options detailed in the layer
management for 10 Mbyte/s Baseband
Repeaters (IEEE 802.3k) standard
s
Fully compatible with the Novell Hub
Management Interface (HMI) specification
s
Provides additional IEEE MAU management
functions (802.3p draft)
s
Interfaces directly with AMD’s Am79C981
Integrated Multiport Repeater Plus™ (IMR+™)
device to build a fully managed repeater
s
Multiple HIMIB/IMR+ devices can be used in a
system
s
8-bit microprocessor interface allows attribute
access, interrupt control, and management
control
s
Maskable interrupts for notification of status/
error reporting
s
Internal “receive only” MAC tracks all address
information and monitors exception conditions
s
Supports mapping of node source addresses to
port numbers, through implementing source
address match function
s
Full 32-bit hardware-implemented counters
incur no additional software overhead to keep
network statistics
s
Pinout allows simple board layout between
IMR+ and HIMIB devices
s
28-pin PLCC device in CMOS technology for low
power with a single +5 V supply
GENERAL DESCRIPTION
The Am79C987 Hardware Implemented Management
Information Base (HIMIB) device is a highly integrated
chip that simplifies building fully managed multiport re-
peaters. The device integrates all the necessary
counters, attributes, actions, and notifications specified
by the Layer Management for 10 Mbyte/s Baseband
Repeaters (IEEE 802.3k) standard, as well as addi-
tional features and enhancements, including functions
specific to 10BASE-T repeaters.
The HIMIB chip is designed to be used in conjunction
with AMD’s Integrated Multiport Repeater Plus (IMR+)
device. When connected to an IMR+ (Am79C981)
device, the HIMIB chip provides complete repeater and
per-port statistics on demand from an 8-bit parallel in-
terface. No external processor is required to keep track
of attributes locally, as full 32-bit counters are provided.
The HIMIB device implements a simple 8-bit micropro-
cessor interface, allowing multiple HIMIB devices to be
used in a system. No additional logic is required for in-
terfacing the HIMIB device to the IMR+ device.
The HIMIB chip is packaged in a 28-pin plastic leaded
chip carrier (PLCC). The device is fabricated in CMOS
technology and requires a single +5 V supply.
Publication#
17305
Rev:
B
Amendment/0
Issue Date:
May 1994
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
1
PRELIMINARY
AMD
BLOCK DIAGRAM
CK
RST
Clock/
Reset
Data
802.3
Receive
MAC
Attributes
Port Number
CRS
STR
DAT
JAM
ACK
COL
D7–0
CS
C/D
RD
WR
RDY
INT
Bus
Interface
Status
IMR+
Management
Port
Interface
SCLK
SI
SO
17305B-1
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Description
Twisted-Pair Ethernet Transceiver (TPEX)
Twisted-Pair Ethernet Transceiver Plus (TPEX+)
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Media Access Controller for Ethernet (MACE
TM
)
Integrated Local Area Communications Controller
TM
(ILACC
TM
)
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+
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Plug n’ Play support)
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PCnet-PCI Single-Chip Ethernet Controller for PCI Local Bus
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Integrated Multiport Repeater Plus
TM
(IMR+
TM
)
Local Area Network Controller for Ethernet (LANCE)
IEEE 802.3/Ethernet/Cheapernet Tap Transceiver
2
Am79C987
P R E L I M I N A R Y
CONNECTION DIAGRAM
PLCC
LOGIC SYMBOL
ACK
COL
RST
CK
V
DD
JAM
DAT
D7–0
4
SCLK
SI
CRS
STR
SO
CS
RD
5
6
7
8
9
10
11
12 13 14 15 16 17 18
WR
D7
RDY
C/D
INT
V
SS
D6
Am79C987
3
2
1 28 27 26
25
24
23
22
21
20
19
D0
D1
D2
D3
V
SS
D4
D5
CS
C/D
RD
WR
RDY
INT
RST
CK
V
SS
V
DD
CRS
STR
SCLK
SI
Am79C987
SO
DAT
JAM
ACK
V
SS
COL
17305B-2
17305B-3
Am79C987
3
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed
by a combination of the elements below.
AM79C987
J
C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
PACKAGE TYPE
J = 28-Pin Plastic Leaded Chip Carrier (PL 028)
SPEED
See Product Selector Guide and Valid Combination
DEVICE NUMBER/DESCRIPTION
Am79C987
Hardware Implemented Management Information Base (HIMIB)
Valid Combinations
AM79C987
JC
Valid Combinations
Valid combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
4
Am79C987
P R E L I M I N A R Y
PIN DESCRIPTION
CK
Clock
Input
CK is the master 20 MHz clock. The IMR+ device X
1
pin
must also be clocked with the identical clock signal.
ACK
Acknowledge
Input, Active LOW
When this input is asserted, it indicates that data on the
DAT and JAM inputs are valid.
COL
Expansion Collision
Input, Active LOW
When this input is asserted, it indicates that there is a
transmit collision because more than one IMR+ device
is active (requesting access to the expansion port).
RST
Reset
Input, Active LOW
Driving this pin LOW resets the internal logic of the
HIMIB. The HIMIB device must be reset with the identi-
cal synchronous RST signal of the IMR+ device.
DAT
Expansion Port Data
Input
When ACK is asserted and JAM is LOW, the expansion
port data consists of the NRZ received data. When
ACK is not asserted, the state of DAT is ignored.
Note:
None of the 32-bit and 48-bit attributes are
cleared upon reset.
SI
Serial Input (to the IMR+ chip)
Output
The SI pin is used to output management port
commands to the IMR+ device. This pin should be con-
nected to the SI pin of the IMR+ chip.
JAM
Jam
Input
When ACK is asserted and JAM is HIGH, an active
IMR+ device is in a collision state. When JAM is as-
serted, the state of DAT will indicate either a multiport
(DAT = 0) or single-port (DAT = 1) collision condition.
When ACK is not asserted, the state of JAM is ignored.
SO
Serial Output (from the IMR+ chip)
Input
The SO pin is used to receive management port infor-
mation from the IMR+ device. This pin should be
connected to the SO pin of the IMR+ chip.
D7–0
Data
Input/Output, 3-State
Data Input/Output pins. These pins are in high-
impedance state if the HIMIB device is not selected.
SCLK
Serial Clock
Output
10 MHz clock used to drive the IMR+ management port
serial clock (SCLK).
C/D
Command/Data
Input
This input pin allows selection of either the Command
or Data port in the HIMIB device. When this signal is
HIGH, the Command port is selected and, when it is
LOW, the Data port is selected. This pin is typically con-
nected to the least significant bit of the address bus.
CRS
Carrier Sense
Input
The CRS pin should be connected to the CRS pin of
the IMR+ device. States of the internal carrier sense
signals of the IMR+ AUI and twisted-pair ports are se-
rially input on this pin continuously.
STR
Store
Output, High Impedance
This pin should be connected to the STR pin of the
IMR+ chip. This pin is an output when the HIMIB device
is interfaced to an IMR+ device; otherwise it remains in
high-impedance state.
WR
Write Strobe
Input, Active LOW
When this pin is asserted and the CS is active, a write
operation is initiated.
RD
Read Strobe
Input, Active LOW
When this pin is asserted and the CS is active, a read
operation is initiated.
Am79C987
5
Microcontroller MCU
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