W3EG72129S-JD3 datasheet, PDF - EEWORLD Datasheet

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W3EG72129S-JD3: Description1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL; File Size172KB，12 Pages; ManufacturerWhite Electronic Designs Corporation; Websitehttp://www.wedc.com/

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W3EG72129S-JD3 Overview

1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL

W3EG72129S-JD3 Preview

White Electronic Designs

W3EG72129S-JD3

PRELIMINARY*

1GB – 2x64Mx72 DDR SDRAM REGISTERED w/PLL

FEATURES

Double-data-rate architecture

Clock speeds of 100MHz, 133MHz, 166MHz and

200MHz

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2,5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto and self refresh

Serial presence detect

Dual Rank

Power Supply:

• V

= V

CCQ

= +2.5V (100, 133 and 166MHz)

• V

= V

CCQ

= +2.6V (200MHz)

JEDEC standard 184 pin DIMM package

PCB height:

• JD3: 30.48mm (1.20")

NOTE: Consult factory for availability of:

• RoHS compliant products

• Vendor source control options

• Industrial temperature option

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

DESCRIPTION

The W3EG72129S is a 2x64Mx72 Double Data Rate

SDRAM memory module based on 512Mb DDR SDRAM

component. The module consists of eighteen 64Mx8 DDR

SDRAMs in 66 pin TSOP package mounted on a 184 Pin

FR4 substrate.

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lenths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

OPERATING FREQUENCIES

DDR400 @CL=3

Clock Speed

CL-t

RCD

-t

200MHz

3-3-3

DDR333 @CL=2.5

166MHz

2.5-3-3

DDR266 @CL=2

133MHz

2-2-2

DDR266 @CL=2

133MHz

2-3-3

DDR266 @CL=2.5

133MHz

2.5-3-3

DDR200 @CL=2

100MHz

2-2-2

October 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

W3EG72129S-JD3

PRELIMINARY

PIN CONFIGURATION

SYMBOL

REF

DQ0

DQ1

DQS0

DQ2

DQ3

RESET#

DQ8

DQ9

DQS1

CCQ

DQ10

DQ11

CKE0

CCQ

DQ16

DQ17

DQS2

DQ18

CCQ

DQ19

DQ24

DQ25

DQS3

DQ26

DQ27

CB0

CB1

SYMBOL

DQS8

CB2

CB3

BA1

DQ32

CCQ

DQ33

DQS4

DQ34

BA0

DQ35

DQ40

CCQ

WE#

DQ41

CAS#

DQS5

DQ42

DQ43

DQ48

DQ49

CCQ

DQS6

DQ50

DQ51

CCID

DQ56

DQ57

DQS7

DQ58

DQ59

SDA

SCL

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

SYMBOL

DQ4

DQ5

CCQ

DQM0

DQ6

DQ7

CCQ

DQ12

DQ13

DQM1

DQ14

DQ15

CKE1

CCQ

DQ20

A12

DQ21

A11

DQM2

DQ22

DQ23

DQ28

DQ29

CCQ

DQM3

DQ30

DQ31

CB4

CB5

CCQ

CK0

CK0#

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

SYMBOL

DQM8

A10

CB6

CCQ

CB7

DQ36

DQ37

DQM4

DQ38

DQ39

DQ44

RAS#

DQ45

CCQ

CS0#

CS1#

DQM5

DQ46

DQ47

CCQ

DQ52

DQ53

DQS15

DQ54

DQ55

CCQ

DQ60

DQ61

DQS16

DQ62

DQ63

CCQ

SA0

SA1

SA2

CCSPD

A0-A12

BA0-BA1

DQ0-DQ63

CB0-CB7

DQS0-DQS8

CK0

CK0#

CKE0, CKE1

CS0#, CS1#

RAS#

CAS#

DQM0-DQM8

WE#

CCQ

REF

CCSPD

SDA

SCL

SA0-SA2

CCID

RESET#

PIN NAMES

Address input (Multiplexed)

Bank Select Address

Data Input/Output

Check bits

Data Strobe Input/Output

Clock Input

Clock Enable input

Chip Select Input

Row Address Strobe

Column Address Strobe

Data-in Mask

Write Enable

Power Supply (2.5V)

Power Supply for DQS (2.5V)

Ground

Power Supply for Reference

Serial EEPROM Power Supply

(2.3V to 3.6V)

Serial data I/O

Serial clock

Address in EEPROM

Indentiﬁcation Flag

No Connect

Reset Enable

October 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

FUNCTIONAL BLOCK DIAGRAM

RCS1#

DQS4

DQM4

CS# DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

CS# DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

W3EG72129S-JD3

PRELIMINARY

DQS0

DQM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

RCS0#

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

CS# DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

CS# DQS

DQS1

DQM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

CS# DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

CS# DQS

DQS5

DQM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

CS# DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

CS# DQS

DQS2

DQM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

CS# DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

CS# DQS

DQS6

DQM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

CS# DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

CS# DQS

DQS3

DQM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

CS# DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

CS# DQS

DQS7

DQM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

CS# DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

CS# DQS

DQS8

DQM8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O7

I/O6

I/O1

I/O0

I/O5

I/O4

I/O3

I/O2

CS# DQS

I/O0

I/O1

I/O6

I/O7

I/O2

I/O3

I/O4

I/O5

CS# DQS

120

CK0

CK0#

PLL

SERIAL PD

CS0#

CS1#

BA0-BA1

A0-A12

RAS#

CAS#

CKE0

CKE1

WE#

PCK

PCK#

RCS0#

RCS1#

RBA0-RBA1

RA0-RA12

RRAS#

RCAS#

RCKE0

RCKE1

RWE#

RESET#

SCL

BA0-BA1: SDRAMs

A0-A12: SDRAMs

RAS#: SDRAMs

CAS#: SDRAMs

CKE: SDRAMs

WE#: DQRAMs

SDA

SA0 SA1 SA2

DDR SDRAM

CCSPD

CCQ

REF

SPD

DDR SDRAMS

Note: All resistor values are 22Ω unless otherwise indicated.

October 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to V

Voltage on V

supply relative to V

Storage Temperature

Power Dissipation

Short Circuit Current

Note:

W3EG72129S-JD3

PRELIMINARY

Symbol

, V

OUT

, V

CCQ

STG

Value

-0.5 to 3.6

-1.0 to 3.6

-55 to +150

Units

°C

Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability

DC CHARACTERISTICS

0°C

≤

70°C, V

= 2.5V ± 0.2V

Symbol

CCQ

REF

Parameter

Supply Voltage

Reference Voltage

Termination Voltage

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Min

2.3

1.15

REF

+ 0.15

-0.3

+ 0.76

—

Max

2.7

1.35

CCQ

+ 0.3

REF

-0.15

—

-0.76

Unit

CAPACITANCE

= 25°C. f = 1MHz, V

= 2.5V

Parameter

Input Capacitance (A0-A12)

Input Capacitance (RAS#,CAS#,WE#)

Input Capacitance (CKE0)

Input Capacitance (CK0#,CK0)

Input Capacitance (CS0#)

Input Capacitance (DQM0-DQM8)

Input Capacitance (BA0-BA1)

Data input/output capacitance (DQ0-DQ63)(DQS)

Data input/output capacitance (CB0-CB7)

Symbol

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT

Max

6.5

5.5

6.5

Unit

October 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

W3EG72129S-JD3

PRELIMINARY

Recommended operating conditions, 0°C

≤

70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V

Includes DDR SDRAM component only

DDR400@

CL=3

Max

4950

DDR333@

CL=2.5

Max

4140

DDR266@

CL=2

Max

4140

DDR266@

CL=2.5

Max

4140

DDR200@

CL=2

Max

4140

SPECIFICATIONS AND TEST CONDITIONS

Parameter

Operating Current

Symbol Conditions

DD0

One device bank; Active - Precharge;

(MIN); t

(MIN); DQ,DM

and DQS inputs changing once per

clock cycle; Address and control

inputs changing once every two

cycles.

One device bank; Active-Read-

Precharge Burst = 2; t

(MIN);

(MIN); l

OUT

= 0mA; Address

and control inputs changing once per

clock cycle.

All device banks idle; Power-down

mode; t

(MIN); CKE=(low)

CS# = High; All device banks idle;

(MIN); CKE = high; Address

and other control inputs changing

once per clock cycle. V

= V

REF

for

DQ, DQS and DM.

One device bank active; Power-

Down mode; t

(MIN); CKE=(low)

CS# = High; CKE = High; One device

bank; Active-Precharge; t

RAS

(MAX); t

(MIN); DQ, DM and

DQS inputs changing twice per clock

cycle; Address and other control

inputs changing once per clock cycle.

Burst = 2; Reads; Continuous burst;

One device bank active; Address

and control inputs changing once

per clock cycle; T

= T

(MIN); l

OUT

= 0mA.

Burst = 2; Writes; Continuous burst;

One device bank active; Address

and control inputs changing once per

clock cycle; t

(MIN); DQ,DM

and DQS inputs changing once per

clock cycle.

= t

(MIN)

CKE

≤

0.2V

Four bank interleaving Reads (BL=4)

with auto precharge with t

(MIN); t

(MIN); Address and

control inputs change only during

Active Read or Write commands.

Units

Operating Current

DD1

5490

4680

Precharge Power-

Down Standby Current

Idle Standby Current

DD2P

DD2F

180

1980

180

1620

180

1620

180

1620

180

1620

rnA

Active Power-Down

Standby Current

Active Standby Current

DD3P

DD3N

1620

2160

1260

1800

1260

1800

1260

1800

1260

1800

Operating Current

DD4R

5580

4770

Operating Current

DD4W

5670

4590

rnA

Auto Refresh Current

Self Refresh Current

Operating Current

DD5

DD6

DD7A

8370

180

10260

7020

180

9090

7020

180

9000

7020

180

9000

7020

180

9000

October 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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W3EG72129S-JD3 Related Products

	W3EG72129S-JD3	W3EG72129S403JD3	W3EG72129S265JD3
Description	1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL	1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL	1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL
Is it Rohs certified?	-	conform to	conform to
Maker	-	White Electronic Designs Corporation	White Electronic Designs Corporation
package instruction	-	DIMM,	DIMM,
Reach Compliance Code	-	unknow	unknow
access mode	-	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	-	0.7 ns	0.75 ns
Other features	-	AUTO/SELF REFRESH; LG-MAX; WD-MAX	AUTO/SELF REFRESH; LG-MAX; WD-MAX
JESD-30 code	-	S-PBGA-B107	S-PBGA-B107
length	-	133.48 mm	133.48 mm
memory density	-	1073741824 bi	1073741824 bi
Memory IC Type	-	DDR DRAM MODULE	DDR DRAM MODULE
memory width	-	8	8
Number of functions	-	1	1
Number of ports	-	1	1
Number of terminals	-	184	184
word count	-	134217728 words	134217728 words
character code	-	128000000	128000000
Operating mode	-	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	-	70 °C	70 °C
organize	-	128MX8	128MX8
Package body material	-	UNSPECIFIED	UNSPECIFIED
encapsulated code	-	DIMM	DIMM
Package shape	-	RECTANGULAR	RECTANGULAR
Package form	-	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	-	NOT SPECIFIED	NOT SPECIFIED
Certification status	-	Not Qualified	Not Qualified
Maximum seat height	-	30.48 mm	30.48 mm
self refresh	-	YES	YES
Maximum supply voltage (Vsup)	-	2.7 V	2.7 V
Minimum supply voltage (Vsup)	-	2.3 V	2.3 V
Nominal supply voltage (Vsup)	-	2.5 V	2.5 V
surface mount	-	YES	YES
technology	-	CMOS	CMOS
Temperature level	-	COMMERCIAL	COMMERCIAL
Terminal form	-	NO LEAD	NO LEAD
Terminal location	-	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	-	NOT SPECIFIED	NOT SPECIFIED
width	-	3.81 mm	3.81 mm

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