White Electronic Designs
WEDPN16M72VR-XB2X
16MX72 REGISTERED SYNCHRONOUS DRAM
FEATURES
Registered for enhanced performance of bus
speeds
• 100, 125, 133**MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 25 x 25mm
Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 16M x 72
Weight: WEDPN16M72VR-XB2X - 2.5 grams
typical
GENERAL DESCRIPTION
The 128MByte (1Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 67,108,864-bit banks is organized as 8,192 rows
by 512 columns by 16 bits. The MCP also incorporates
two 16-bit universal bus drivers for input control signals
and addresses.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 1Gb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n
rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
The 1Gb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along
with a power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation,
the ability to interleave between internal banks in order
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access.
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
BENEFITS
59% SPACE SAVINGS
Reduced part count
Reduced I/O count
• 40% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Glueless connection to memory controller/PCI
bridge
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
* This product is subject to change without notice.
** Available at commercial and industrial temperatures only.
January 2005
Rev. 1
White Electronic Designs
WEDPN16M72VR-XB2X
FIGURE 1 – PIN CONFIGURATION
Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ
1
2
DQ
0
3
DQ
14
4
DQ
15
5
V
SS
6
V
SS
7
A
9
8
A
10
9 10 11 12 13 14 15 16
A
11
A
8
V
CC
V
CC
DQ
16
DQ
17
DQ
31
V
SS
DQ
2
DQ
12
DQ
13
V
SS
V
SS
A
0
A
7
A
6
A
1
V
CC
V
CC
DQ
18
DQ
19
DQ
29
DQ
30
DQ
3
DQ
4
DQ
10
DQ
11
V
CC
V
CC
A
2
A
5
A
4
A
3
V
SS
V
SS
DQ
20
DQ
21
DQ
27
DQ
28
DQ
6
DQ
5
DQ
8
DQ
9
V
CC
V
CC
A
12
DNU
DNU
DNU
V
SS
V
SS
DQ
22
DQ
23
DQ
26
DQ
25
DQ
7
DQMB0
V
CC
DQMB1
NC
NC
NC
BA
0
BA
1
NC
NC
NC
DQMB2
V
SS
NC
DQ
24
CAS#
WE#
V
CC
CLK
0
NC
NC
OE#
V
SS
DQMB3
CLK
1
CS
0
#
RAS#
V
CC
CKE
NC
NC
CS
1
#
V
SS
NC
LE#
V
SS
V
SS
V
CC
V
CC
V
SS
V
CC
V
SS
Vss
V
CC
V
CC
V
SS
V
SS
V
CC
V
CC
V
SS
V
CC
V
SS
V
SS
V
CC
V
CC
NC
NC
V
CC
NC
NC
NC
NC
V
SS
NC
DNU*
NC
NC
V
CC
NC
NC
NC
CLK
2
V
SS
NC
NC
DQ
56
DQMB7
V
CC
NC
DQMB6
NC
DQMB9
NC
NC
NC
NC
NC
DQMB5
V
SS
DQMB4
DQ
39
DQ
57
DQ
58
DQ
55
DQ
54
NC
NC
DQ
73
DQ
72
DQ
71
DQ
70
DQMB8
NC
DQ
41
DQ
40
DQ
37
DQ
38
DQ
60
DQ
59
DQ
53
DQ
52
V
SS
V
SS
DQ
75
DQ
74
DQ
69
DQ
68
V
CC
V
CC
DQ
43
DQ
42
DQ
36
DQ
35
DQ
62
DQ
61
DQ
51
DQ
50
V
CC
V
CC
DQ
77
DQ
76
DQ
67
DQ
66
V
SS
V
SS
DQ
45
DQ
44
DQ
34
DQ
33
Vss
DQ
63
DQ
49
DQ
48
V
CC
V
CC
DQ
79
DQ
78
DQ
65
DQ
64
V
SS
V
SS
DQ
47
DQ
46
DQ
32
V
CC
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
DNU* Pin K16 is reserved for optional CS2# pinout (CS# of U4). Contact factory for information.
January 2005
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WEDPN16M72VR-XB2X
FIGURE 2 FUNCTIONALIN BLOCK DIAGRAM
WE
B
#
RAS
B
#
CAS
B
#
WE# RAS# CAS#
A
0-12
DQ
0
BA
0-1
•
CLK
0
CKE
B
CS
0B
#
DQMB
0B
DQMB
1B
CLK
CKE
CS#
DQML
DQMH
DQ
0
U0
•
•
•
•
•
DQ
15
•
•
•
•
•
•
DQ
15
74ALVC16334
A
0-12
BA
0-
BA
1
WE# RAS# CAS#
A
0-12
BA
0-1
DQ
0
DQ
16
U5
CLK
2
OE#
LE#
CLK
OE#
LE#
CLK
0
CKE
B
CS
1B
#
DQMB
2B
DQMB
3B
CLK
CKE
CS#
DQML
DQMH
U1
•
•
•
•
•
•
DQ
15
•
•
•
•
•
•
DQ
31
DQMB
0-9
WE#
CKE
RAS#
CAS#
CS
0-1
#
74ALVC16334
DQMB
0B-9B
WE
B
#
CKE
B
RAS
B
#
CAS
B
#
CS
0B-1B
#
WE# RAS# CAS#
A
0-12
BA
0-1
CLK
1
CKE
B
CS
0B
#
DQMB
4B
DQMB
5B
CLK
CKE
CS#
DQML
DQMH
DQ
0
DQ
32
U6
CLK
OE#
LE#
U2
•
•
•
•
•
•
DQ
15
•
•
•
•
•
•
DQ
47
WE# RAS# CAS#
A
0-12
DQ
0
BA
0-1
•
CLK
1
CKE
B
CS
1B
#
DQMB
6B
DQMB
7B
CLK
CKE
CS#
DQML
DQMH
DQ
48
U3
•
•
•
•
•
DQ
15
•
•
•
•
•
•
DQ
63
WE# RAS# CAS#
A
0-12
BA
0-1
CLK
0
CKE
B
CS
0B
#
DQMB
8B
DQMB
9B
CLK
CKE
CS#
DQML
DQMH
DQ
0
DQ
64
U4
•
•
•
•
•
•
DQ
15
•
•
•
•
•
•
DQ
79
January 2005
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-12 select the row). The address bits (A0-8) registered
coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
WEDPN16M72VR-XB2X
Figure 3. The Mode Register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use. Address A12 (M12) is
undefined but should be driven LOW during loading of the
mode register.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown
in Figure 3. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are available for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-8 when the burst length is set to two; by A2-8 when
the burst length is set to four; and by A3-8 when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified
may result in undefined operation. Once power is applied
to V
CC
and V
CCQ
(simultaneously) and the clock is stable
(stable clock is defined as a signal cycling within timing
constraints specified for the clock pin), the SDRAM
requires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100µs period and continuing at
least through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for Mode Register
programming. Because the Mode Register will power up
in an unknown state, it should be loaded prior to applying
any operational command.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selec-tion of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
January 2005
Rev. 1
4
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIGURE 3 – MODE REGISTER DEFINITION
Burst
Length
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
WEDPN16M72VR-XB2X
TABLE 1 – BURST DEFINITION
Starting Column
Address
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
Order of Accesses Within a Burst
Type = Sequential
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
Type = Interleaved
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
2
Mode Register (Mx)
Unused Reserved* WB Op Mode
CAS Latency
BT
Burst Length
*Should program
M12, M11, M10 = 0, 0, 0
to ensure compatibility
with future devices.
M2 M1M0
0
0
0
0
1
1
1
1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
2
4
8
Burst Length
M3 = 0
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
4
Reserved
Reserved
Reserved
Full Page
8
M3
0
1
Burst Type
Sequential
Interleaved
M6 M5 M4
0
0
0
0
1
1
1
1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Full
Page
(y)
A1
0
0
1
1
A2
A1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
n = A0-9/8/7
(location 0-y)
M8
0
-
M7
0
-
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
M9
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
NOTES:
1. For full-page accesses: y = 512.
2. For a burst length of two, A1-8 select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the starting
column within the block.
4. For a burst length of eight, A3-8 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-8 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-8 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
January 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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