PIPELINED ARCHITECTURE, ALSO CONFIGURABLE AS 1M X 18, OR 512K X 36
JESD-30 code
R-PBGA-B159
length
22 mm
memory density
18874368 bi
Memory IC Type
SRAM MODULE
memory width
72
Number of functions
1
Number of terminals
159
word count
262144 words
character code
256000
Operating mode
SYNCHRONOUS
Maximum operating temperature
125 °C
Minimum operating temperature
-55 °C
organize
256KX72
Package body material
PLASTIC/EPOXY
encapsulated code
BGA
Package shape
RECTANGULAR
Package form
GRID ARRAY
Parallel/Serial
PARALLEL
Peak Reflow Temperature (Celsius)
NOT SPECIFIED
Certification status
Not Qualified
Maximum seat height
2.2 mm
Maximum supply voltage (Vsup)
3.6 V
Minimum supply voltage (Vsup)
3.135 V
Nominal supply voltage (Vsup)
3.3 V
surface mount
YES
technology
CMOS
Temperature level
MILITARY
Terminal form
BALL
Terminal pitch
1.27 mm
Terminal location
BOTTOM
Maximum time at peak reflow temperature
NOT SPECIFIED
width
14 mm
WEDPY256K72V-100BM Preview
White Electronic Designs
256Kx72 Synchronous Pipeline SRAM
FEATURES
Fast clock speed: 100, 133, 150, 166
and 200** MHz
Fast access time: 5.0, 4.0, 3.8, 3.5, 3.1ns
+3.3V power supply (V
CC
)
+2.5V output buffer supply (V
CCQ
)
Single-cycle deselect
Common data inputs and data outputs
Clock-controlled and registered addresses, data
I/Os and control signals
SNOOZE MODE for reduced-power standby
Individual BYTE WRITE control and GLOBAL
WRITE
Six chip enables for simple depth expansion and
address pipeline
Internally self-timed WRITE cycle
Burst control (interleaved or linear burst)
Packaging:
159-bump PBGA package, 14mm x 22mm
Commercial, industrial, and military temperature
ranges
User configurable as 512K x 36, or 1M x 18
**200 MHz for commercial and industrial temperature only.
SA
0-17
ADSC#
ADSP#
ADV#
BWa#
BWb#
BWc#
BWd#
BWE#
CS1
1
#
CS2
1
#
CS2
1
CLK
GW#
MODE
OE
1#
ZZ
WEDPY256K72V-XBX
DESCRIPTION
The WEDPY256K72V-XBX employs high-speed, low-
power CMOS designs that are fabricated using an
advanced CMOS process. The 16Mb Synchronous
SRAMs integrate two 256K x 36 SRAMs into a single
PBGA package to provide 256K x 72 configuration. All
synchronous inputs are controlled by a positive-edge-
triggered single-clock input (CLK). The synchronous inputs
include all addresses, all data inputs, and active LOW chip
selects (CS#). Asynchronous inputs include the output
enable (OE1#/OE2#), clock (CLK).
* This product is subject to change without notice.
FIGURE 1 – BLOCK DIAGRAM
256Kx36
A
0-17
SSRAM
ADSC#
ADSP#
ADV#
BWa#
BWb#
BWc#
BWd#
WE#
DQ
0-35
CS
1
#
CS
2
#
CS
2
CLK
GW#
MODE
OE#
ZZ
IC1
DQ
0-35
BWe#
BWf#
BWg#
BWh#
CS1
1
#
CS2
2
#
CS2
2
OE
2
#
A
0-17
ADSC#
ADSP#
ADV#
BWa#
BWb#
BWc#
BWd#
WE#
CS
1
#
CS
2
#
CS
2
CLK
GW#
MODE
OE#
ZZ
256Kx36
SSRAM
IC2
DQ
36-71
August 2004
Rev. 7
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
—
ADV#
OE1#
CS21#
BWc#
CS2
1
CS1
1
#
DQ26
SA17
SA16
SA14
SA15
OE2#
BWE#
BWh#
CS1
2
#
2
DQ16
DQ17
ADSP#
CLK
BWb#
DQ18
DQ19
DQ20
DQ21
DQ52
DQ51
DQ53
ADSC#
CS2
2
#
BWg#
CS2
2
3
DQ14
DQ15
GW#
BWa#
BWd#
DQ22
DQ23
DQ24
DQ25
DQ49
DQ50
DQ48
DQ47
DQ46
BWf#
DQ62
4
DQ12
DQ11
DQ13
GND
GND
V
CC
GND
V
CCQ
V
CC
GND
V
CC
GND
V
CCQ
DQ45
BWe#
DQ54
5
DQ10
DQ9
DNU
GND
V
CC
V
CCQ
V
CC
V
CCQ
V
CC
V
CCQ
GND
GND
V
CC
GND
DQ56
DQ55
6
ZZ
DQ7
GND
V
CC
GND
GND
V
CCQ
V
CC
V
CCQ
V
CC
V
CCQ
V
CC
GND
DNU
DQ60
DQ57
7
WEDPY256K72V-XBX
8
DQ4
DQ3
DQ2
SA11
SA8
DQ30
DQ31
DQ28
DQ27
DQ40
DQ42
DQ43
MODE
DQ64
DQ65
DQ63
9
DQØ
DQ1
SA12
SA9
SA7
DQ34
DQ33
DQ32
DQ39
DQ38
DQ41
SA3
SA2
DQ66
DQ69
DQ67
10
DQ8
SA13
SA10
SA6
SAØ
SA1
SA5
DQ35
DQ37
DQ36
DQ44
DNU
SA4
DQ70
DQ71
DQ68
DQ6
DQ5
DQ29
V
CCQ
GND
V
CC
GND
V
CC
V
CCQ
GND
V
CC
GND
GND
DQ59
DQ61
DQ58
DNU = DO NOT USE. RESERVED FOR FUTURE UPGRADES.
August 2004
Rev. 7
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WEDPY256K72V-XBX
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
First Address (External)
X...X00
X...X01
X...X10
X...X11
Second Address (Internal)
X...X01
X...X00
X...X11
X...X10
Third Address (Internal)
X...X10
X...X11
X...X00
X...X01
Fourth Address (Internal)
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
First Address (External)
X...X00
X...X01
X...X10
X...X11
Second Address (Internal)
X...X01
X...X10
X...X11
X...X00
Third Address (Internal)
X...X10
X...X11
X...X00
X...X01
Fourth Address (Internal)
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (X36)
Function
READ
READ
WRITE Byte "a"
WRITE All Bytes
WRITE All Bytes
GW#
H
H
H
H
L
BWE#
H
L
L
L
X
BWa#
X
H
L
L
X
BWb#
X
H
H
L
X
BWc#
X
H
H
L
X
BWd#
X
H
H
L
X
NOTE:
1. Using BWE# and BWa# through BWd#, any one or more bytes may be written.
2. Insert BWe# through BWh# for DQ36-71 control.
August 2004
Rev. 7
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
TRUTH TABLE
Operation
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Address Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CS1
H
L
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CS2
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CS2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
WEDPY256K72V-XBX
ADV
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
H
L-H
L-H
L-H
DQ
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
Q
HIGH Z
D
Q
HIGH Z
Q
HIGH Z
Q
HIGH Z
D
D
Q
HIGH Z
Q
HIGH Z
D
D
NOTE:
1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or WE#) are LOW or GW# is
LOW. WRITE# = H for all BWx#, BWE#, GW# High.
3. BWa enables WRITEs to DQ0-8. BWb# enables WRITEs to DQ9-17. BWc enables WRITEs to DQ18-26. BWd# enables
WRITE to DQ27-35.
4. All inputs excepts OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending bursts.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be held in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
August 2004
Rev. 7
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
Supply relative to V
SS
Voltage on V
CCQ
Supply relative to V
SS
V
IN
(DQx)
V
IN
(Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
-0.5V to +4.6V
-0.5V to +4.6V
-0.5V to V
CCQ
+0.5V
-0.5V to V
CC
+0.5V
-55°C to +150°C
100 mA
WEDPY256K72V-XBX
* Stress greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
-55°C
≤
T
A
≤
+125°C
Description
Input High (Logic 1)Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Ouptut Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Output Buffer Supply
Symbol
V
IH
V
IHQ
V
IL
I
LI
I
LO
V
OH
V
OL
V
CC
V
CCQ
Conditions
Inputs
Data (DQ)
0V ≤ V
IN
≤ V
CC
Outputs disabled, 0V ≤ V
IN
≤ V
CCQ
(DQX)
I
OH
= -1.0mA
I
OL
= 1.0mA
Min
1.7
1.7
-0.3
-2.0
-1.0
2.0
—
3.135
2.375
Max
V
CC
+0.3
V
CCQ
+0.3
0.7
2.0
1.0
—
0.4
3.6
2.9
Units
V
V
V
µA
µA
V
V
V
V
Notes
1
1
1
2
1
1
1
1
NOTES:
1. All voltages referenced to Vss (GND).
DC CHARACTERISTICS
-55°C
≤
T
A
≤
+125°C
Description
Power Supply
Current: Operating
CMOS Standby
Clock Running
I
DD
I
SB2
I
SB4
Conditions
Device selected; All inputs
≤
V
IL
or
≥
V
IH
; Cycle
time
≥
t
KC
MIN; V
CC
= MAX; Outputs open
Device deselected; V
CC
= MAX; All inputs
≤
Vss
+ 0.2
Device deselected; V
CC
= MAX; All inputs
≤
Vss +
0.2 or
≥
V
CC
-0.2; Cycle time
≥
t
KC
MIN; ADSC#,
ADSP#, GW#, BWx#, ADV#,
≥
V
IH
100 MHz 133 MHz 150 MHz 160 MHz 200 MHz
600
20
170
750
20
180
950
20
220
950
20
220
1050
20
240
Units
mA
mA
mA
Notes
1.2
2
2
NOTES:
1. I
DD
is specified with no output current and increases with faster cycle times. I
DD
increases with faster cycle times and greater output loading.
2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device is active (not in power-down mode).
BGA CAPACITANCE
T
A
= +25°C, F = 1MHz
Description
Control Input Capacitance
Common Control Input Capacitance (2)
Input/Output Capacitance (DQ)
Address Capacitance (SA)
Clock Capacitance (CLK)
Symbol Max Units Notes
CI
6
pF
1
CIC
15
pF
1
CO
10
pF
1
CsA
15
pF
1
C
CK
12
pF
1
BGA THERMAL RESISTANCE
Description
Junction to Ambient (No Airflow)
Junction to Ball
Junction to Case (Top)
Symbol Max
Theta JA 30.5
Theta JB 17.3
Theta JC 9.8
Units Notes
0
C/W
1
0
C/W
1
0
C/W
1
NOTE 1: Refer to BGA Thermal Resistance Correlation application note at www.wedc.
com in the application notes section for modeling conditions.
NOTES:
1. This parameter is guaranteed by design but not tested.
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