82V2051EPPG8 datasheet, PDF - EEWORLD Datasheet

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82V2051EPPG8: DescriptionTelecom Interface ICs 3.3V LH SINGLE LIU; Categorysemiconductor Analog mixed-signal IC; File Size632KB，61 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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Telecom Interface ICs 3.3V LH SINGLE LIU

82V2051EPPG8 Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	IDT (Integrated Device Technology, Inc.)
Product Category	Telecom Interface ICs
RoHS	Details
Product	E1 Line Interface Units - LIUs
Packaging	Reel
NumOfPackaging	1
Factory Pack Quantity	500

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SINGLE CHANNEL E1 SHORT

HAUL LINE INTERFACE UNIT

FEATURES

•

Single channel E1 short haul line interfaces

Supports HPS (Hitless Protection Switching) for 1+1 protection

without external relays

Single 3.3 V power supply with 5 V tolerance on digital interfaces

Meets or exceeds specifications in

ANSI T1.102

- ITU I.431, G.703, G.736, G.775 and G.823

- ETSI 300-166, 300-233 and TBR12/13

Software programmable or hardware selectable on:

- Wave-shaping templates

- Line terminating impedance (75

Ω/120 Ω)

- Adjustment of arbitrary pulse shape

- JA (Jitter Attenuator) position (receive path or transmit path)

- Single rail/dual rail system interfaces

- HDB3/AMI line encoding/decoding

- Active edge of transmit clock (TCLK) and receive clock (RCLK)

- Active level of transmit data (TDATA) and receive data (RDATA)

- Receiver or transmitter power down

IDT82V2051E

•

- High impedance setting for line drivers

- PRBS (Pseudo Random Bit Sequence) generation and detection

with 2

-1 PRBS polynomials

- 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS error

counter

- Analog loopback, Digital loopback, Remote loopback

Short circuit protection and internal protection diode for line

drivers

AIS (Alarm Indication Signal) detection

Supports serial control interface, Motorola and Intel Multiplexed

interfaces and hardware control mode

Pin compatibe to 82V2081 T1/E1/J1 Long Haul/Short Haul LIU

and 82V2041E T1/E1/J1 Short Haul LIU

Package:

Available in 44-pin TQFP packages

Green package options available

DESCRIPTION

The IDT82V2051E is a single channel E1 Line Interface Unit. The

IDT82V2051E performs clock/data recovery, AMI/HDB3 line decoding and

detects and reports the LOS conditions. An integrated Adaptive Equalizer

is available to increase the receive sensitivity and enable programming of

LOS levels. In transmit path, there is an AMI/HDB3 encoder and Waveform

Shaper. There is one Jitter Attenuator, which can be placed in either the

receive path or the transmit path. The Jitter Attenuator can also be disabled.

The IDT82V2051E supports both Single Rail and Dual Rail system inter-

faces. To facilitate the network maintenance, a PRBS generation/detection

circuit is integrated in the chip, and different types of loopbacks can be set

according to the applications. Two different kinds of line terminating imped-

ance, 75

Ω

and 120

Ω

are selectable. The chip also provides driver short-

circuit protection and internal protection diode. The chip can be controlled

by either software or hardware.

The IDT82V2051E can be used in LAN, WAN, Routers, Wireless Base

Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,

CSU/DSU equipment, etc.

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.



2005 Integrated Device Technology, Inc.

December 9, 2005

DSC-6528/2

Table of Contents

IDT82V2051E Pin Configurations ............................................................................................... 8

Pin Description ............................................................................................................................ 9

Functional Description .............................................................................................................. 15

3.1

Control Mode Selection .................................................................................................... 15

3.2

Transmit Path ................................................................................................................... 15

3.2.1 Transmit Path System Interface.............................................................................. 15

3.2.2 Encoder.................................................................................................................. 15

3.2.3 Pulse Shaper .......................................................................................................... 15

3.2.3.1 Preset Pulse Templates .......................................................................... 15

3.2.3.2 User-Programmable Arbitrary Waveform ................................................ 16

3.2.4 Transmit Path Line Interface................................................................................... 17

3.2.5 Transmit Path Power Down .................................................................................... 17

3.3

Receive Path .................................................................................................................... 18

3.3.1 Receive Internal Termination .................................................................................. 18

3.3.2 Line Monitor ............................................................................................................ 19

3.3.3 Adaptive Equalizer .................................................................................................. 20

3.3.4 Receive Sensitivity.................................................................................................. 20

3.3.5 Data Slicer .............................................................................................................. 20

3.3.6 CDR (Clock & Data Recovery)................................................................................ 20

3.3.7 Decoder .................................................................................................................. 20

3.3.8 Receive Path System Interface............................................................................... 21

3.3.9 Receive Path Power Down ..................................................................................... 21

3.4

Jitter Attenuator ................................................................................................................ 21

3.4.1 Jitter Attenuation Function Descripton .................................................................... 21

3.4.2 Jitter Attenuator Performance ................................................................................. 22

3.5

Los And AIS Detection ...................................................................................................... 22

3.5.1 LOS Detection......................................................................................................... 22

3.5.2 AIS Detection .......................................................................................................... 23

3.6

Transmit And Detect Internal Patterns .............................................................................. 24

3.6.1 Transmit All Ones ................................................................................................... 24

3.6.2 Transmit All Zeros................................................................................................... 24

3.6.3 PRBS Generation And Detection............................................................................ 24

3.7

Loopback .......................................................................................................................... 24

3.7.1 Analog Loopback .................................................................................................... 24

3.7.2 Digital Loopback ..................................................................................................... 24

3.7.3 Remote Loopback................................................................................................... 24

3.8

Error Detection/Counting And Insertion ............................................................................ 27

Table of Contents

December 9, 2005

IDT82V2051E

SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

3.9

3.10

3.11

3.12

3.13

3.14

3.15

3.8.1 Definition Of Line Coding Error ............................................................................... 27

3.8.2 Error Detection And Counting ................................................................................. 27

3.8.3 Bipolar Violation And PRBS Error Insertion ............................................................ 28

Line Driver Failure Monitoring ........................................................................................... 28

MCLK And TCLK .............................................................................................................. 29

3.10.1 Master Clock (MCLK).............................................................................................. 29

3.10.2 Transmit Clock (TCLK) ........................................................................................... 29

Microcontroller Interfaces ................................................................................................. 30

3.11.1 Parallel Microcontroller Interface ............................................................................ 30

3.11.2 Serial Microcontroller Interface ............................................................................... 30

Interrupt Handling ............................................................................................................. 30

5V Tolerant I/O Pins ......................................................................................................... 31

Reset Operation ................................................................................................................ 31

Power Supply .................................................................................................................... 31

Programming Information ........................................................................................................ 32

4.1

Register List And Map ...................................................................................................... 32

4.2

Reserved Registers .......................................................................................................... 32

4.3

Register Description ......................................................................................................... 33

4.3.1 Control Registers .................................................................................................... 33

4.3.2 Transmit Path Control Registers............................................................................. 35

4.3.3 Receive Path Control Registers.............................................................................. 37

4.3.4 Network Diagnostics Control Registers .................................................................. 39

4.3.5 Interrupt Control Registers...................................................................................... 41

4.3.6 Line Status Registers.............................................................................................. 43

4.3.7 Interrupt Status Registers ....................................................................................... 45

4.3.8 Counter Registers ................................................................................................... 46

Hardware Control Pin Summary .............................................................................................. 47

Test Specifications .................................................................................................................... 49

Microcontroller Interface Timing Characteristics ................................................................... 56

7.1

Serial Interface Timing ...................................................................................................... 56

7.2

Parallel Interface Timing ................................................................................................... 57

Table of Contents

December 9, 2005

List of Tables

Table-1

Table-2

Table-3

Table-4

Table-5

Table-6

Table-7

Table-8

Table-9

Table-10

Table-11

Table-12

Table-13

Table-14

Table-15

Table-16

Table-17

Table-18

Table-19

Table-20

Table-21

Table-22

Table-23

Table-24

Table-25

Table-26

Table-27

Table-28

Table-29

Table-30

Table-31

Table-32

Table-33

Table-34

Table-35

Table-36

Table-37

Table-38

Table-39

Table-40

Table-41

List of Tables

Pin Description ................................................................................................................ 9

Transmit Waveform Value For E1 75 ohm.................................................................... 16

Transmit Waveform Value For E1 120 ohm.................................................................. 16

Impedance Matching for Transmitter ............................................................................ 17

Impedance Matching for Receiver ................................................................................ 18

Criteria of Starting Speed Adjustment........................................................................... 22

LOS Declare and Clear Criteria, Adaptive Equalizer Disabled ..................................... 22

LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 23

AIS Condition ................................................................................................................ 23

Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 24

EXZ Definition ............................................................................................................... 27

Interrupt Event............................................................................................................... 31

Register List and Map ................................................................................................... 32

ID: Device Revision Register ........................................................................................ 33

RST: Reset Register ..................................................................................................... 33

GCF: Global Configuration Register ............................................................................. 33

TERM: Transmit and Receive Termination Configuration Register .............................. 33

JACF: Jitter Attenuation Configuration Register ........................................................... 34

TCF0: Transmitter Configuration Register 0 ................................................................. 35

TCF1: Transmitter Configuration Register 1 ................................................................. 35

TCF2: Transmitter Configuration Register 2 ................................................................. 35

TCF3: Transmitter Configuration Register 3 ................................................................. 36

TCF4: Transmitter Configuration Register 4 ................................................................. 36

RCF0: Receiver Configuration Register 0..................................................................... 37

RCF1: Receiver Configuration Register 1..................................................................... 37

RCF2: Receiver Configuration Register 2..................................................................... 38

MAINT0: Maintenance Function Control Register 0...................................................... 39

MAINT1: Maintenance Function Control Register 1...................................................... 39

MAINT6: Maintenance Function Control Register 6...................................................... 39

INTM0: Interrupt Mask Register 0 ................................................................................. 41

INTM1: Interrupt Masked Register 1 ............................................................................. 41

INTES: Interrupt Trigger Edge Select Register ............................................................. 42

STAT0: Line Status Register 0 (real time status monitor)............................................. 43

STAT1: Line Status Register 1 (real time status monitor)............................................. 44

INTS0: Interrupt Status Register 0 ................................................................................ 45

INTS1: Interrupt Status Register 1 ................................................................................ 45

CNT0: Error Counter L-byte Register 0......................................................................... 46

CNT1: Error Counter H-byte Register 1 ........................................................................ 46

Hardware Control Pin Summary ................................................................................... 47

Absolute Maximum Rating ............................................................................................ 49

Recommended Operation Conditions ........................................................................... 49

December 9, 2005

82V2051EPPG8 Related Products

	82V2051EPPG8	82V2051EPP
Description	Telecom Interface ICs 3.3V LH SINGLE LIU	Telecom Interface ICs 3.3V LH SINGLE LIU
Product Attribute	Attribute Value	Attribute Value
Manufacturer	IDT (Integrated Device Technology, Inc.)	IDT (Integrated Device Technology, Inc.)
Product Category	Telecom Interface ICs	Telecom Interface ICs
RoHS	Details	N
Product	E1 Line Interface Units - LIUs	E1 Line Interface Units - LIUs
Packaging	Reel	Tube
NumOfPackaging	1	1
Factory Pack Quantity	500	80

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