PHK24NQ04LT
TrenchMOS™ logic level FET
M3D315
Rev. 01 — 12 September 2003
Product data
1. Product profile
1.1 Description
N-channel logic level field-effect transistor in a plastic package using TrenchMOS™
technology.
Product availability:
PHK24NQ04LT in SOT96-1 (SO8).
1.2 Features
s
Logic level compatible
s
Low gate charge.
1.3 Applications
s
DC-to-DC converters
s
Switched-mode power supplies.
1.4 Quick reference data
s
V
DS
≤
40 V
s
P
tot
≤
6.25 W
s
I
D
≤
21.2 A
s
R
DSon
≤
7.7 mΩ.
2. Pinning information
Table 1:
Pin
1,2,3
4
Pinning - SOT96-1 (SO8) simplified outline and symbol
Description
source (s)
gate (g)
8
5
d
Simplified outline
Symbol
5,6,7,8 drain (d)
g
1
Top view
4
MBK187
MBB076
s
SOT96-1 (SO8)
Philips Semiconductors
PHK24NQ04LT
TrenchMOS™ logic level FET
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
sp
= 25
°C
peak source (diode forward) current T
sp
= 25
°C;
pulsed; t
p
≤
10
µs
T
sp
= 25
°C;
V
GS
= 10 V;
Figure 2
and
3
T
sp
= 80
°C;
V
GS
= 10 V;
Figure 2
T
sp
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
sp
= 25
°C;
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
25
°C ≤
T
j
≤
150
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−55
−55
-
-
Max
40
40
±20
21.2
15.9
60
6.25
+150
+150
5.2
20.8
Unit
V
V
V
A
A
A
W
°C
°C
A
A
Source-drain diode
9397 750 11709
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 — 12 September 2003
2 of 12
Philips Semiconductors
PHK24NQ04LT
TrenchMOS™ logic level FET
120
Pder
(%)
80
03aa17
120
Ider
(%)
80
03aa25
40
40
0
0
50
100
150
Tsp (°C)
200
0
0
50
100
150
200
Tsp (
°
C)
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
I
D
I
der
=
-------------------
×
100%
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
102
Limit RDSon = VDS / ID
ID
(A)
03aj99
tp = 10
µs
100
µs
10
1 ms
10 ms
DC
1
100 ms
10-1
10-1
1
10
VDS (V)
102
T
sp
= 25
°C;
I
DM
is single pulse; V
GS
= 10 V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 11709
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 — 12 September 2003
3 of 12
Philips Semiconductors
PHK24NQ04LT
TrenchMOS™ logic level FET
4. Thermal characteristics
Table 3:
R
th(j-sp)
Thermal characteristics
Conditions
Min Typ Max Unit
-
-
20
K/W
thermal resistance from junction to solder point
Figure 4
Symbol Parameter
4.1 Transient thermal impedance
102
Zth(j-sp)
(K/W)
03aj98
10
δ
= 0.5
0.2
0.1
0.05
1
0.02
P
δ
=
tp
T
tp
single pulse
10-1
10-4
10-3
10-2
10-1
T
t
1
10
tp (s)
102
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 11709
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 — 12 September 2003
4 of 12
Philips Semiconductors
PHK24NQ04LT
TrenchMOS™ logic level FET
5. Characteristics
Table 4:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
°C
T
j
= 150
°C
T
j
=
−55 °C
I
DSS
drain-source leakage current
V
DS
= 40 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
V
GS
=
±16
V; V
DS
= 0 V
V
GS
= 4.5 V; I
D
= 12 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 150
°C
V
GS
= 10 V; I
D
= 14 A;
Figure 7
and
8
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 2.3 A; V
GS
= 0 V;
Figure 12
reverse recovery time
recovered charge
I
S
= 2 A; dI
S
/dt =
−100
A/µs; V
GS
= 0 V
V
DD
= 20 V; I
D
= 1 A; V
GS
= 5 V; R
G
= 6
Ω
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
Figure 11
I
D
= 14 A; V
DD
= 20 V; V
GS
= 10 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
-
-
-
64
7.7
11.5
490
240
30
30
60
40
0.75
49
36
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
-
7.8
14
6.5
9.2
16.6
7.7
mΩ
mΩ
mΩ
-
-
-
0.05
-
10
1
500
100
µA
µA
nA
1
0.6
-
1.5
-
-
2
-
2.2
V
V
V
40
36
-
-
-
-
V
V
Conditions
Min
Typ
Max
Unit
2985 -
Source-drain diode
9397 750 11709
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 — 12 September 2003
5 of 12
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