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70V06L55PF8

Description
SRAM 16Kx8, 128K 3.3V DUAL-PORT RAM
Categorystorage   
File Size688KB,24 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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70V06L55PF8 Overview

SRAM 16Kx8, 128K 3.3V DUAL-PORT RAM

70V06L55PF8 Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIDT (Integrated Device Technology, Inc.)
Product CategorySRAM
RoHSN
Memory Size128 kbit
Organization16 k x 8
Access Time55 ns
Interface TypeParallel
Supply Voltage - Max3.6 V
Supply Voltage - Min3 V
Supply Current - Max155 mA
Minimum Operating Temperature0 C
Maximum Operating Temperature+ 70 C
Mounting StyleSMD/SMT
Package / CaseTQFP-64
PackagingReel
Height1.4 mm
Length14 mm
Memory TypeSDR
TypeAsynchronous
Width14 mm
Moisture SensitiveYes
NumOfPackaging1
Factory Pack Quantity750
Unit Weight0.012720 oz
HIGH-SPEED 3.3V
16K x 8 DUAL-PORT
STATIC RAM
Features
IDT70V06S/L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns (max.)
Low-power operation
– IDT70V06S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V06L
Active: 380mW (typ.)
Standby: 660µW (typ.)
IDT70V06 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
13L
A
0L
(1,2)
,
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
A
13R
A
0R
(1,2)
Address
Decoder
14
MEMORY
ARRAY
14
Address
Decoder
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
INT
R
(2)
2942 drw 01
AUGUST 2015
1
DSC-2942/10
©2015 Integrated Device Technology, Inc.
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