FemtoClock® NG Universal Frequency
Translator
ICS840N202I
DATA SHEET
General Description
The ICS840N202I is a highly flexible FemtoClock® NG general
purpose, low phase noise Frequency Translator / Synthesizer with
alarm and monitoring functions suitable for networking and
communications applications. It is able to generate any output
frequency in the 1MHz - 250MHz range (see Table 3 for details). A
wide range of input reference clocks and a range of low-cost
fundamental mode crystal frequencies may be used as the source
for the output frequency.
The ICS840N202I has three operating modes to support a very
broad spectrum of applications:
1) Frequency Synthesizer
Features
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•
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Fourth generation FemtoClock® NG technology
Universal Frequency Translator/Frequency Synthesizer
Two LVCMOS/LVTTL outputs
•
•
•
•
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•
Both outputs may be set to use 2.5V or 3.3V output levels
Programmable output frequency: 1.0MHz to 250MHz
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
Input frequency range: 8kHz - 710MHz
Crystal input frequency range: 16MHz - 40MHz
Two factory-set register configurations for power-up default state
•
•
Synthesizes output frequencies from a 16MHz - 40MHz
fundamental mode crystal.
Fractional feedback division is used, so there are no
requirements for any specific crystal frequency to produce the
desired output frequency with a high degree of accuracy.
•
•
•
•
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Power-up default configuration pin or register selectable
Configurations customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I
2
C
I
2
C Serial interface for register programming
2) High-Bandwidth Frequency Translator
•
•
•
Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation, so it will not attenuate much jitter on the input
reference.
Applications: Networking & Communications.
Translates any input clock in the 8kHz - 710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external crystal to provide
significant jitter attenuation.
RMS phase jitter at 125MHz, using a 40MHz crystal
(12kHz - 20MHz): 616fs (typical), Low Bandwidth Mode (FracN)
Output supply voltage modes:
V
DD
/V
DDA
/V
DDO
3.3V/3.3V/3.3V
3.3V/3.3V/2.5V
2.5V/2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
3) Low-Bandwidth Frequency Translator
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•
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Pin Assignment
CLK_ACTIVE
XTALBAD
CLK1BAD
HOLDOVER
CLK0BAD
GND
V
DDA
This device provides two factory-programmed default power-up
configurations burned into One-Time Programmable (OTP) memory.
The configuration to be used is selected by the CONFIG pin. The two
configurations are specified by the customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices. The two configurations may be completely independent of
one another.
One usage example might be to install the device on a line card with
two optional daughter cards: an OC-3 option (configuration 0)
requiring a 155.52MHz clock translated from a 19.44MHz input and
a Gigabit Ethernet option (configuration 1) requiring a 125MHz clock
translated from the same 19.44MHz input reference.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured. However, these settings
would have to be re-written each time the device powers-up.
LF1
LF0
XTAL_IN
XTAL_OUT
V
DD
CLK_SEL
CLK0
nCLK0
V
DD
GND
CLK1
nCLK1
1
2
3
4
5
6
7
8
9
10
40 39 38 37 36 35 34 33 32 31
30
29
nc
LOCK_IND
V
DD
OE0
GND
Q0
V
DDO
Q1
GND
OE1
GND
ICS840N202I
40 Lead VFQFN
6mm x 6mm x 0.925mm
K Package
Top View
28
27
26
25
24
23
22
21
11 12 13 14 15 16 17 18 19 20
CONFIG
S_A1
S_A0
Rsvd
PLL_BYPASS
SDATA
SCLK
Rsvd
V
DD
nc
ICS840N202CKI REVISION A NOVEMBER 1, 2013
1
©2013 Integrated Device Technology, Inc.
ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Complete Block Diagram
PLL_BYPASS
XTAL
XTAL_IN
XTA L_OUT
OSC
PD/LF
FemtoClock® NG
VCO
1995 - 2600 MHz
Feedback Divider
÷M_INT
[7:0]
1
Output Divider
÷N[10:0]
Q0
OE0
0
÷M_FRAC
[17:0]
Q1
OE1
LF1
ADC
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
POR
÷4
0
1
R
3
÷M1[16:0]
PD/CP
÷P[16:0]
LF0
R
S
C
3
C
P
Control Logic
Global Registers
OTP
Register Set 0
Register Set 1
0
1
C
S
Status Indicators
CLK_ACTIVE
LOCK_IND
XTALBAD
CLK0BAD
CLK1BAD
HOLDOVER
SCLK, S_A0, S_A1
SDATA
CONFIG
ICS840N202CKI REVISION A NOVEMBER 1, 2013
2
©2013 Integrated Device Technology, Inc.
ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3, 7, 13, 29
4
5
6
8, 21, 23, 27,
35
9
10
11, 32
12
14
15
Name
XTAL_IN
XTAL_OUT
V
DD
CLK_SEL
CLK0
nCLK0
GND
CLK1
nCLK1
nc
PLL_BYPASS
SDATA
SCLK
Input
Power
Input
Input
Input
Power
Input
Input
Unused
Input
I/O
Input
Pulldown
Pullup
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Crystal oscillator interface designed for 12pF parallel resonant crystals.
XTAL_IN (pin 1) is the input and XTAL_OUT (pin 2) is the output.
Core supply pins. All must be either 3.3V or 2.5V.
Input clock select. Selects the active differential clock input.
0 = CLK0, nCLK0 (default)
1 = CLK1, nCLK1
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating (set by the
internal pullup and pulldown resistors).
Power supply pins.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating (set by the
internal pullup and pulldown resistors).
No connect. These pins are to be left unconnected.
Bypasses the VCXO PLL.
0 = PLL NOT bypassed (default)
1 = PLL Bypassed
I
2
C Data Input/Output. Open drain. LVCMOS/LVTTL Interface Levels.
I
2
C Clock Input. LVCMOS/LVTTL Interface Levels.
Configuration Pin. Selects between one of two factory programmable pre-set
power-up default configurations. The two configurations can have different
output/input frequency translation ratios, different PLL loop bandwidths, etc.
These default configurations can be overwritten after power-up via I
2
C if the
user so desires.
0 = Configuration 0 (default)
1 = Configuration 1
I
2
C Address Bit 1. LVCMOS/LVTTL Interface Levels.
I
2
C Address Bit 0. LVCMOS/LVTTL Interface Levels.
Reserved for future use. Should be left unconnected.
Pullup
Active High Output Enable for Q1.
0 = Output pins high-impedance
1 = Output switching (default)
Clock output. LVCMOS/LVTTL Interface Levels.
Output supply voltage. Either 2.5V or 3.3V.
Clock output. LVCMOS/LVTTL Interface Levels.
Pullup
Active High Output Enable for Q0.
0 = Output pins high-impedance
1 = Output switching (default)
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
Indicates which of the two differential clock inputs is currently selected.
0 - CLK0, nCLK0 differential input pair
1 - CLK1, nCLK1 differential input pair
3
©2013 Integrated Device Technology, Inc.
16
CONFIG
Input
Pulldown
17
18
19, 20
22
24
25
26
28
S_A1
S_A0
Rsvd
OE1
Q1
V
DDO
Q0
OE0
Input
Input
Reserved
Input
Output
Power
Output
Input
Pulldown
Pulldown
30
LOCK_IND
Output
31
CLK_ACTIVE
Output
ICS840N202CKI REVISION A NOVEMBER 1, 2013
ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Table 1. Pin Descriptions
Number
33, 34
36
Name
LF0, LF1
V
DDA
Input
Power
Type
Description
Loop filter connection node pins. LF0 is the output. LF1 is the input.
Analog supply voltage. See Applications section for details on how to connect
this pin.
Alarm output reflecting if the device is in a holdover state. LVCMOS/LVTTL
interface levels.
0 = Device is locked to a valid input reference
1 = Device is not locked to a valid input reference
Alarm output reflecting the state of CLK0. LVCMOS/LVTTL interface levels.
0 = Input Clock 0 is switching within specifications
1 = Input Clock 0 is out of specification
Alarm output reflecting the state of CLK1. LVCMOS/LVTTL interface levels.
0 = Input Clock 1 is switching within specifications
1 = Input Clock 1 is out of specification
Alarm output reflecting the state of XTAL. LVCMOS/LVTTL interface levels.
0 = crystal is switching within specifications
1 = crystal is out of specification
37
HOLDOVER
Output
38
CLK0BAD
Output
39
CLK1BAD
Output
40
XTALBAD
Output
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
Parameter
Input
Capacitance
XTAL_IN, XTAL_OUT,
PLL_BYPASS, CONFIG,
A0, A1, OE0, OE1, SCLK
Test Conditions
Minimum
Typical
4
8
51
51
15
Maximum
Units
pF
pF
k
k
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Q0, Q1
R
OUT
Output
Impedance
CLK_ACTIVE,
HOLDOVER, XTALBAD,
CLK0BAD, CLK1BAD,
LOCK_IND
25
ICS840N202CKI REVISION A NOVEMBER 1, 2013
4
©2013 Integrated Device Technology, Inc.
ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Functional Description
The ICS840N202I is designed to provide two copies of almost any
desired output frequency within its operating range (0.98 - 250MHz)
from any input source in the operating range (8kHz - 710MHz). It is
capable of synthesizing frequencies from a crystal or crystal
oscillator source. The output frequency is generated regardless of
the relationship to the input frequency. The output frequency will be
exactly the required frequency in most cases. In most others, it will
only differ from the desired frequency by a few ppb. IDT configuration
software will indicate the frequency error, if any. The ICS840N202I
can translate the desired output frequency from one of two input
clocks. Again, no relationship is required between the input and
output frequencies in order to translate to the output clock rate. In this
frequency translation mode, a low-bandwidth, jitter attenuation option
is available that makes use of an external fixed-frequency crystal or
crystal oscillator to translate from a noisy input source. If the input
clock is known to be fairly clean or if some modulation on the input
needs to be tracked, then the high-bandwidth frequency translation
mode can be used, without the need for the external crystal.
The input clock references and crystal input are monitored
continuously and appropriate alarm outputs are raised both as
register bits and hard-wired pins in the event of any
out-of-specification conditions arising. Clock switching is supported
in manual, revertive & non-revertive modes.
The ICS840N202I has two factory-programmed configurations that
may be chosen from as the default operating state after reset. This is
intended to allow the same device to be used in two different
applications without any need for access to the I
2
C registers. These
defaults may be over-written by I
2
C register access at any time, but
those over-written settings will be lost on power-down. Please
contact IDT if a specific set of power-up default settings is desired.
level on the CONFIG pin which would select different divider ratios
within the ICS840N202I for the two different card configurations.
Access via I
2
C would not be necessary for operation using either of
the internal configurations.
Operating Modes
The ICS840N202I has three operating modes which are set by the
MODE_SEL[1:0] bits. There are two frequency translator modes -
low bandwidth and high bandwidth and a frequency synthesizer
mode. The device will operate in the same mode regardless of which
configuration is active.
Please make use of IDT-provided configuration applications to
determine the best operating settings for the desired configurations
of the device.
Output Dividers & Supported Output Frequencies
In all 3 operating modes, the output stage behaves the same way, but
different operating frequencies can be specified in the two
configurations.
The internal VCO is capable of operating in a range anywhere from
1.995GHz - 2.6GHz. It is necessary to choose an integer multiplier of
the desired output frequency that results in a VCO operating
frequency within that range. The output divider stage N[10:0] is
limited to selection of even integers from 10 to 2046. Please refer to
Table 3 for the values of N applicable to the desired output frequency.
Table 3. Output Divider Settings & Frequency Ranges
Register
Setting
Nn[10:0]
00000000000 -
0000000100x
0000000101x
0000000110x
0000000111x
0000001000x
0000001001x
...
1111111111x
Frequency
Divider
N
2-8
10
12
14
16
18
Even N
2046
Minimum
f
OUT
(MHz)
Maximum
f
OUT
(MHz)
Configuration Selection
The ICS840N202I comes with two factory-programmed default
configurations. When the device comes out of power-up reset the
selected configuration is loaded into operating registers. The
ICS840N202I uses the state of the CONFIG pin or CONFIG register
bit (controlled by the CFG_PIN_REG bit) to determine which
configuration is active. When the output frequency is changed either
via the CONFIG pin or via internal registers, the output behavior may
not be predictable during the register writing and output settling
periods. Devices sensitive to glitches or runt pulses may have to be
reset once reconfiguration is complete.
Once the device is out of reset, the contents of the operating registers
can be modified by write access from the I
2
C serial port. Users that
have a custom configuration programmed may not require I
2
C
access.
It is expected that the ICS840N202I will be used almost exclusively
in a mode where the selected configuration will be used from device
power-up without any changes during operation. For example, the
device may be designed into a communications line card that
supports different I/O modules such as a standard OC-3 module
running at 155.52MHz or a (255/237) FEC rate OC-3 module running
at 167.332MHz. The different I/O modules would result in a different
ICS840N202CKI REVISION A NOVEMBER 1, 2013
5
Not Supported
199.5
166.3
142.5
124.7
110.8
1995 / N
0.98
260 (Note 1)
216.7
185.7
162.5
144.4
2600 / N
1.27
Note 1: using a divider setting of N = 0x00A or 0x00B with a high
VCO frequency can result in the CMOS output running faster than its
250MHz maximum operating frequency.
Frequency Synthesizer Mode
This mode of operation allows an arbitrary output frequency to be
generated from a fundamental mode crystal input. As can be seen
from the block diagram in Figure 1, only the upper feedback loop is
used in this mode of operation.
©2013 Integrated Device Technology, Inc.
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