MC100LVEL14
3.3 V ECL 1:5 Clock
Distribution Chip
Description
The MC100LVEL14 is a low skew 1:5 clock distribution chip
designed explicitly for low skew clock distribution applications. The
device can be driven by either a differential or single-ended ECL or, if
positive power supplies are used, PECL input signal. The LVEL14 is
functionally and pin compatible with the EL14 but is designed to
operate in ECL or PECL mode for a voltage supply range of
−3.0
V to
−3.8
V ( or 3.0 V to 3.8 V).
The LVEL14 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high speed
system clock. When LOW (or left open and pulled LOW by the input
pulldown resistor) the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore all associated specification limits are referenced to the
negative edge of the clock input.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and
V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking to 0.5
mA. When not used, V
BB
should be left open.
Features
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20
1
SOIC−20 WB
DW SUFFIX
CASE 751D−05
MARKING DIAGRAM
20
100LVEL14
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
•
•
•
•
•
•
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
ESD Protection: Human Body Model > 2 kV
The 100 Series Contains Temperature Compensation
ORDERING INFORMATION
Device
MC100LVEL14DWG
Package
SOIC−20 WB
(Pb-Free)
Shipping†
38 Units / Tube
PECL Mode Operating Range:
V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
•
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
−3.0
V to
−3.8
V
•
Internal Input Pulldown Resistors on CLK
MC100LVEL14DWR2G SOIC−20 WB 1000 Tape & Reel
(Pb-Free)
•
•
•
•
Q Output will Default LOW with Inputs Open or at V
EE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity: Level 3 (Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure,
BRD8011/D.
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
•
Transistor Count = 303 Devices
•
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
©
Semiconductor Components Industries, LLC, 2016
July, 2016
−
Rev. 10
1
Publication Order Number:
MC100LVEL14/D
MC100LVEL14
V
CC
20
EN
19
V
CC
NC SCLK CLK CLK V
BB
SEL V
EE
18
17
16
15
1 0
D
Q
14
13
12
11
Table 1. PIN DESCRIPTION
PIN
CLK, CLK
SCLK
EN
SEL
Q
0−4,
Q
0−4
FUNCTION
ECL Diff Clock Inputs
ECL Scan Clock Input
ECL Sync Enable
ECL Clock Select Input
ECL Diff Clock Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
1
Q0
2
Q0
3
Q1
4
Q1
5
Q2
6
Q2
7
Q3
8
Q3
9
Q4
10
Q4
V
BB
V
CC
V
EE
NC
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Pinout
(Top View)
and Logic Diagram
Table 2. FUNCTION TABLE
CLK
L
H
X
X
X
SCLK
X
X
L
H
X
SEL
L
L
H
H
X
EN
L
L
L
L
H
Q
L
H
L
H
L*
*On next negative transition of CLK or SCLK
X = Don’t Care
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
Wave Solder
0 lfpm
500 lfpm
Standard Board
< 2 to 3 sec @ 260°C
SOIC−20 WB
SOIC−20 WB
SOIC−20 WB
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
≤
V
CC
V
I
≥
V
EE
Condition 2
Rating
8 to 0
−8
to 0
6 to 0
−6
to 0
50
100
±0.5
−40
to +85
−65
to +150
90
60
30 to 35
265
Unit
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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MC100LVEL14
Table 4. LVPECL DC CHARACTERISTICS
(V
CC
= 3.3 V; V
EE
= 0 V (Note 1))
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
V
PP
<
500 mV
V
PP
≥
500 mV
Input HIGH Current
Input LOW Current
Others
CLK
0.5
−300
2215
1470
2135
1490
1.92
Min
Typ
32
2295
1605
Max
40
2420
1745
2420
1825
2.04
2275
1490
2135
1490
1.92
Min
25°C
Typ
32
2345
1595
Max
40
2420
1680
2420
1825
2.04
2275
1490
2135
1490
1.92
Min
85°C
Typ
34
2345
1595
Max
42
2420
1680
2420
1825
2.04
Unit
mA
mV
mV
mV
mV
V
V
1.3
1.5
2.9
2.9
150
0.5
−300
1.2
1.4
2.9
2.9
150
0.5
−300
1.2
1.4
2.9
2.9
150
mA
mA
I
IH
I
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min
and 1.0 V.
Table 5. LVNECL DC CHARACTERISTICS
(V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 1))
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
V
PP
<
500 mV
V
PP
≥
500 mV
Input HIGH Current
Input LOW Current
Others
CLK
0.5
−300
−1085
−1830
−1165
−1810
−1.38
Min
Typ
32
−1005
−1695
Max
40
−880
−1555
−880
−1475
−1.26
−1025
−1810
−1165
−1810
−1.38
Min
25°C
Typ
32
−955
−1705
Max
40
−880
−1620
−880
−1475
−1.26
−1025
−1810
−1165
−1810
−1.38
Min
85°C
Typ
34
−955
−1705
Max
42
−880
−1620
−880
−1475
−1.26
Unit
mA
mV
mV
mV
mV
V
V
−2.0
−1.8
−0.4
−0.4
150
0.5
−300
−2.1
−1.9
−0.4
−0.4
150
0.5
−300
−2.1
−1.9
−0.4
−0.4
150
mA
mA
I
IH
I
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min
and 1.0 V.
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MC100LVEL14
Table 5. AC CHARACTERISTICS
(V
CC
= 3.3 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 1)
−40°C
Symbol
f
max
t
PLH
t
PHL
t
SKEW
t
JITTER
t
S
t
H
V
PP
t
r
t
f
Characteristic
Maximum Toggle Frequency (Figure 2)
Prop
Delay
Part-to-Part Skew
Within-Device Skew (Note 2)
Random Clock Jitter (RMS) @ 1 Ghz
(Figure 2)
Setup Time EN
Hold Time EN
Input Swing CLK (Note 3)
Output Rise/Fall Times Q (20%−80%)
0
250
150
230
0.2
−95
150
1000
500
CLK to Q (Diff)
CLK to Q (SE)
SCLK to Q
520
470
470
Min
Typ
>1
720
770
770
200
50
<1
0
250
150
230
0.2
−110
160
1000
500
580
530
530
Max
Min
25°C
Typ
>1
680
680
680
780
830
830
200
50
<1
0
250
150
230
0.2
−125
175
1000
500
630
580
580
Max
Min
85°C
Typ
>1
830
880
880
200
50
<1
Max
Unit
GHz
ps
ps
ps
ps
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. V
EE
can vary
±0.3
V.
2. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions.
3. V
PP
(min) is minimum input swing for which AC parameters guaranteed.
900
800
V
OUTpp
(mV)
700
600
500
400
300
200
100
0
(JITTER)
9
8
7
6
5
4
3
2
1
1500
1800
2100
2400
JITTER
OUT
ps (RMS)
0
300
600
900
1200
FREQUENCY (MHz)
Figure 2. F
max
/Jitter
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ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
MC100LVEL14
Q
Driver
Device
Q
Z
o
= 50
W
50
W
50
W
D
Z
o
= 50
W
D
Receiver
Device
V
TT
V
TT
= V
CC
−
2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note
AND8020/D
−
Termination of ECL Logic Devices)
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPSt I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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