ispPAC30
In-System Programmable Analog Circuit
October 2002
Data Sheet
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Features
■
Flexible Interface and Programming Control
•
•
•
•
Full configuration capability, SPI or JTAG modes
Unlimited device updates using SRAM register
E
2
CMOS
®
for non-volatile configuration storage
Real-time microcontroller configuration/control
High impedance: differential or single-ended
0V to 2.8V with programmable gains (±1 to ±10)
Dual multiplexers (pin or serial port controlled)
Connects easily to existing system circuits
Functional Block Diagram
IN1+ 13
Vref1
12 VS
11 ENSPI
IA
OA
IA
MDAC
Filter
Amplify
Integrate
Compare
IN1- 14
IN2+ 15
Input/Output Routing Pool
Summation Routing Pool
■
Four Input Instrumentation Amplifiers (IA’s)
•
•
•
•
10 TMS
9 TDO
8 TDI
7 TCK
6 CS
IN2- 16
VREFOUT
17
■
Two Configurable Rail-to-Rail Output Amps
•
•
•
•
Single-ended, 0V to 5V output swing
Gain bandwidth product >15MHz
Amplifier,
filter,
integrator or comparator modes
7
filter
frequencies (50kHz to 600kHz)
OUT1 18
OUT2 19
SCOM 20
MDAC
IA
OA
IA
Filter
Amplify
Integrate
Compare
5 MSEL1
4 MSEL2
3 CAL
■
Two 4-Quadrant, 8-Bit Multiplying DACs
IN3+ 21
Vref2
• Full bandwidth when used as a multiplier
• Precision gain (<0.01 steps) with signal as input
• Precision offset (in 7 ranges) using internal Vref
•
•
•
•
Routing of all I/O to any IA or MDAC
Any IA/MDAC summed to either output amplifier
Circuits with and without feedback possible
Routable to maintain pin location relationships
IN3- 22
IN4+ 23
IN4- 24
JTAG/SPI
Interface Logic
& Configuration
Memory
2 PD
Auto-Calibration
■
Analog Input/Summation Routing Pools
1 GND
2.5V Reference
ispPAC30 24-Pin SOIC
■
Other Product Features
•
•
•
•
•
•
•
•
•
Single supply (+5V) operation
Precision voltage reference output (2.5V)
Power-down for
µWatt
power consumption
Auto-calibration of internal offsets
Available in 28-pin PDIP or 24-pin SOIC
Reconfigurable or adaptive signal conditioning
Analog front end for most A/D converters
Programmable analog signal control loops
Precision programmable gain amplifiers
Description
The ispPAC
®
30 is a member of the Lattice family of In-
System Programmable (ISP™) analog integrated cir-
cuits. It is digitally configured via SRAM and utilizes
E
2
CMOS memory for non-volatile storage of its configu-
ration. The
flexibility
of ISP enables programming, verifi-
cation and unlimited reconfiguration, directly on the
printed circuit board.
The ispPAC30 is a complete front end solution for data
acquisition applications using 10 to 12-bit ADC's. It pro-
vides multiple single-ended or differential signal inputs,
multiplexing, precision gain, offset adjustment,
filtering,
and comparison functionality. It also has complete
routability of inputs or outputs to any input cell and then
from any input cell to either summing node of the two
output amplifiers. Designers configure the ispPAC30
and verify its performance using PAC-Designer
®
, an
easy to use, Microsoft Windows
®
compatible develop-
ment tool. Device programming is supported using PC
parallel port I/O operations.
1
pac30_01
■
Applications
Vin1
Vin2
Vin3
ispPAC30
Dual
12-Bit
ADC
µController
www.latticesemi.com
Lattice Semiconductor
ispPAC30 Data Sheet
Electrical Characteristics
TA = 25°C; V
S
= 5.0V; 0V < V
IN
< 2.8V; Gain = 1; Output load = 50pf, 1k
Ω
. IA1, IA2, MDAC1 connected to OA1 and IA3, IA4,
MDAC2 connected to OA2. V
OUT
biased to swing from 0.5 to 4.5V. Auto-Cal initiated immediately prior. (Unless other-
wise specified).
Symbol
Analog Input
V
IN±
(1)
V
OS
(3)
∆V
OS
/
∆T
R
IN
C
IN
I
B
e
N
V
OH
V
OL
I
SC
I
OUT
G
Input Voltage Range
Differential Offset Voltage
(Input Referred)
Differential Offset Drift
Input Resistance
Input Capacitance
Input Bias Current (at DC)
Input Noise Voltage Density
Output Voltage Swing High
Output Voltage Swing Low
Short Circuit Current
Maximum Output Current
Programmable Gain Range
Gain Error
Input Gain Matching
∆
G/
∆
T
PSR
VREF
OUT
IREF
OUT
Gain Drift
Power Supply Rejection
Reference Output Range
Reference Output Current
Reference Output Drift
Reference Output Noise
Power Supply Rejection
Comparator Mode Performance
Comparator Switching Time
Overload Recovery Time
10mV overdrive
100mV overdrive
2.8V overload
4.0
2.5
3.0
µs
µ
s
µ
s
at 25
°C
at 85
°
C
At 10kHz, referred to input, G=10
I
L
= 250
µA
I
L
= 5mA
I
L
= -250
µA
I
L
= -5mA
Short to ground; V
OUT
= 4.9V
See graph in typical performance curves
Individual input amplifier gain
V
OUT
= 0.5V to 4.5V
Any two inputs; any output
-40
°
C to +85
°
C
at 10kHz
Nominally 2.500V; I
LOAD
= 0
(VREF
OUT
change = -1%) source
(VREF
OUT
change = +1%) sink
-40 to +85
°C
100kHz bandwidth
1kHz
-0.2
40
-350
100
40
80
0
1
1
35
74
0.2
25
4.95
4.50
Analog Output
4.97
4.65
0.03
0.11
35
±30
20
3
3
0.05
0.15
V
V
V
V
mA
mA
dB
%
%
ppm/
°
C
dB
%
µA
µ
A
ppm/
°C
µ
V
RMS
dB
Applied to either V
IN+
or V
IN-
2 |V
IN+
- V
IN-
|
G=1
G = 10
-40
°C
to +85
°C;
Any gain, input referred
1
100
50
10
9
2
1
200
70
0
2.8
5.6
2
V
V
mV
µ
V
µV/°C
Ω
pF
pA
pA
nV/ Hz
V
IN-DIFF
(2) Differential Voltage Swing
Parameter
Condition
Min.
Typ.
Max.
Units
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Static Performance
Reference Output (VREF
OUT
)
2
Lattice Semiconductor
ispPAC30 Data Sheet
Electrical Characteristics, Continued
TA = 25°C; V
S
= 5.0V; 0V < V
IN
< 2.8V; Gain = 1; Output load = 50pf, 1k
Ω
. IA1, IA2, MDAC1 connected to OA1 and IA3, IA4,
MDAC2 connected to OA2. V
OUT
biased to swing from 0.5 to 4.5V. Auto-Cal initiated immediately prior. (Unless other-
wise specified).
Symbol
Parameter
Resolution
INL
DNL
V
OS
Integral Non-Linearity
Differential Non-Linearity
Offset Voltage
Gain Error
Input Bandwidth (F
3dB
)
Internal Voltage Reference Performance
V
REF1
/V
REF2
Voltage Output
64mV Setting
128mV Setting
256mV Setting
512mV Setting
1024mV Setting
2048mV Setting
2.500V Setting
Dynamic Performance
SNR
THD
CMR
BW
BW
FP
SR
t
S
Signal to Noise (4)
Total Harmonic Distortion
V
OUT
= 4Vpk (0.5V to 4.5V)
Common Mode Rejection
(V
IN
= 0V to 2.8V) (5)
Small Signal Bandwidth
Full Power Bandwidth
Slew Rate
Settling Time, 0.1%
V
OUT
= 4Vpk (0.5V to 4.5V)
Crosstalk (6)
Filter Characteristics
F
C
|F
C
|
∆F
C
/
∆T
Digital I/O
V
IL
V
IH
Input Low Voltage
Input High Voltage
0
2
0.8
V
S
V
V
Corner Frequency Range (7)
Corner Frequency Accuracy
Corner Frequency Drift
Deviation from calculated -3db point
-40
°C
+ 0 +85
°C
49
3
0.05
619
5
kHz
%
%/
°C
0.1Hz to 114kHz
F
IN
= 10kHz
F
IN
= 100kHz
10kHz
100kHz
All gains, minimum feedback capacitor
All gains
All gains
4V output step, low to high
4V output step, high to low
R
L
= 1k
Ω,
F
IN
= 10kHz
10
1
83
-85
-75
75
65
1.57
1.1
15
2
4
-100
4
8
-74
-60
dB
dB
dB
dB
dB
MHz
MHz
V/
µ
s
µs
µ
s
dB
56
120
246
500
1000
2000
64
128
256
512
1024
2048
72
136
266
524
1048
2096
mV
mV
mV
mV
mV
mV
V
V
IN
= 3Vp-p; V
CM
= 1.4V±0.75V
1.25
1
1.6
Guaranteed monotonic
Condition
Min.
7+sign
0.25
0.5
-1
3
3
Typ.
Max.
Units
bits
lsb
lsb
mV
%
MHz
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
MDAC PACell Performance
2.450 2.500 2.550
3
Lattice Semiconductor
ispPAC30 Data Sheet
Electrical Characteristics, Continued
TA = 25°C; V
S
= 5.0V; 0V < V
IN
< 2.8V; Gain = 1; Output load = 50pf, 1k
Ω
. IA1, IA2, MDAC1 connected to OA1 and IA3, IA4,
MDAC2 connected to OA2. V
OUT
biased to swing from 0.5 to 4.5V. Auto-Cal initiated immediately prior. (Unless other-
wise specified).
Symbol
Digital I/O (Continued)
I
IL
, I
IH
Input Leakage Current
Hysteresis
V
OL
V
OH
Output Low Voltage (TDO)
Output High Voltage (TDO)
Erase/Reprogram Cycles
Calibration Cycle Time
Power Supplies
V
S
I
S
P
D
Operating Supply Voltage
Supply Current (8)
Power Dissipation (9)
Power Down Supply Current
Wakeup Time
Temperature Range
Operation
Storage
-40
-65
85
150
°C
°C
V
S
= 5.0V
V
S
= 5.0V
V
S
= 5.0V
Time to resume normal operation
4.75
5
10
50
10
3.5
5.25
15
75
30
5.0
V
mA
mW
µA
µs
No pull-up/pull-down
With pull-up/pull-down (8)
Schmitt Trigger
I
OL
= 4.0mA
I
OH
= -1.0mA
For E
2
CMOS cells
Initial turn on
Subsequent user initiated
2.4
10K
1M
140
50
250
100
250
0.4
10
±50
µA
µ
A
mV
V
V
cycles
ms
Parameter
Condition
Min.
Typ.
Max.
Units
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Programming and Calibration
Notes:
1. Inputs larger than this will be clipped.
2. Inputs can be used fully differential if care is taken to offset signals so as to not force the outputs below 0V or above V
S
. The total input
swing is measured from one differential extreme, with respect to polarity, to the other, or twice the peak single-ended input range.
3. To insure full spec performance, an auto-calibration should be performed after initial turn-on when the device reaches thermal stability.
4. For all gains except G=1, output is assumed to be driven to 5V by the input signal level (V
IN
x Gain = 5V). When G=1, the maximum single
ended input possible is 2.8V. The consequence is an output of 2.8V instead of 5V. Computed SNR is then 5dB less because of the lower
effective signal. With a true differential 2.5V input and G=1, output will again be a full 5V and SNR will be equal to the value shown in the
specification table.
5. V
IN+
and V
IN-
are connected together for this test.
6. Measured between analog outputs, with an identical signal path configuration used for each. One channel is driven with a 10kHz signal and
the other is not (input grounded).
7. Computed 3db corner frequencies are 619kHz, 401kHz, 250kHz, 169kHz, 114kHz, 74kHz and 49kHz. Actual values found in PAC-
Designer software.
8. Logic inputs will exhibit positive current configured with a pull-down and negative current with a pull-up.
9. Configured so all internal circuitry is powered on.
4
Lattice Semiconductor
ispPAC30 Data Sheet
Pin Descriptions
Pins
PDIP
15, 16, 17, 18,
25, 26, 27, 28
SOIC
13, 14, 15, 16,
21, 22, 23, 24
Symbol
IN
Name
Inputs 1, 2, 3, 4 (+ or -)
Plus or Minus
Description
Differential input pins, with two pins per input
(e.g., IN2+ and IN2-). Each are components of
V
IN
, where differential V
IN
= V
IN+
- V
IN-
.
Multiplexer logic input pin. Selects either of two
analog channels to IA1 (instrument amplifier).
Programmable pull-up, pull-down (default), or
none.
Multiplexer logic input pin. Selects either of two
analog channels to IA4 (instrument amplifier).
Programmable pull-up, pull-down (default), or
none.
Single-ended output pins. Internal feedback to
inputs accommodated.
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
6
5
MSEL1
Multiplexer 1 Control
4
4
MSEL2
Multiplexer 2 Control
21, 22
20
18, 19
17
OUT
VREFOUT
Outputs 1 and 2
Internal voltage reference output pin (+2.5V
Voltage Reference Output nominal). Must be bypassed to GND with a 1µF
capacitor.
Enable SPI Mode
Test Mode Select
Test Data Out
Test Data In
Test Clock
Chip Select
Auto-Calibrate
Power Down
Enable SPI logic input pin. When high, causes
serial port to run in SPI mode. Programmable
pull-up or pull-down (default).
Serial interface logic mode select pin (input).
JTAG interface mode only. Internal pull-up.
Serial interface logic pin (output) for both JTAG
and SPI operation modes. Programmable slew
rate, high or low (default).
Serial interface logic pin (input) for both JTAG
and SPI modes. Internal pull-up.
Serial interface logic clock pin (input) for both
JTAG and SPI modes. Programmable pull-up,
pull-down (default), or none.
Chip select logic input pin. SPI data transfer
enabled by this input. Internal pull-up.
Digital pin (input). Commands an auto-calibration
sequence on a rising edge. Internal pull-down.
Power down enable logic pin (input). Shuts down
all power to device. Programmable pull-up
(default), pull-down or none.
Analog supply pin (5V nominal). Should be
bypassed to GND with 1µF and .01µF capaci-
tors.
Ground pin. Should normally be connected to
the analog ground plane.
Analog signal common pin (sense). Always con-
nected to GND. Auto-calibration accuracy is
determined with respect to this pin.
No internal connections are made to these pins
in the PDIP package.
13
12
11
9
8
7
3
2
11
10
9
8
7
6
3
2
ENSPI
TMS
TDO
TDI
TCK
CS
CAL
PD
14
1
23
5, 10, 19, 24
12
1
20
—
VS
GND
SCOM
NC
Supply Voltage
Ground
Signal Common
No Connects
5
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