Rev 0; 7/07
I
2
C, 32-Bit, Binary Counter Clock with 64-Bit ID
General Description
The DS1372 is a 32-bit binary up counter and 24-bit
down counter with a unique 64-bit ID. The counters, ID,
configuration, and status registers are accessed using
an I
2
C serial interface. The DS1372 includes a
SQW/INT open-drain output that can output either a
square wave at one of four predefined frequencies, or it
can output an active-low signal when the 24-bit down
counter reaches 0.
Features
♦
Compliant with Microsoft Windows Media
®
DRM
10 for Portable Devices
♦
32-Bit Binary Counter
♦
Programmable Alarm
♦
64-Bit Factory-Programmed ID
♦
Interrupt Output
♦
I
2
C Serial Interface
♦
Two Selectable I
2
C Addresses
♦
2.4V to 5.5V Operating Voltage Range
♦
1.3V to 5.5V Timekeeping Operating Range
♦
-40°C to +85°C Operating Temperature Range
♦
8-Pin µSOP
DS1372
Applications
Portable Audio and Video Players
Pin Configuration
TOP VIEW
X1
X2
AD0
GND
1
2
3
4
Ordering Information
+
8
7
V
CC
SQW/INT
SCL
SDA
PART
DS1372U+
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
8 μSOP
DS1372
TOP
MARK
1372
6
5
μSOP
+Denotes
a lead-free package. This symbol also appears on the
top mark.
Windows Media is a registered trademark of Microsoft Corp.
Typical Operating Circuit
V
CC
CRYSTAL
V
CC
V
CC
R
PU
R
PU
SCL
X1
X2 V
CC
SQW/INT
CPU
SDA
R
PU
= t
R
/ C
B
DS1372
GND
AD0
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
I
2
C, 32-Bit, Binary Counter Clock with 64-Bit ID
DS1372
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground…. .-0.3V to +6.0V
Continuous Power Dissipation (T
A
= +70°C)
(derate 4.5mW/°C above +70°C) ……………………. ....360mW
Operating Temperature Range
(noncondensing)……. .......................................-40°C to +85°C
Storage Temperature Range…………………….-55°C to +125°C
Soldering Temperature………….......See IPC/JEDEC J-STD-020
specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.4V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
Supply Voltage
Active Supply Current
Standby Current
(Oscillator Enabled)
Data Retention
(Oscillator Disabled)
Input Logic 1
AD0, SCL, SDA
Input Logic 0
AD0, SCL, SDA
Input Leakage
AD0, SCL, SDA, SQW/INT
Output Logic 0
SYMBOL
V
CC
I
CCA
I
CCS
I
DDR
V
IH
V
IL
I
LI
I
OL
CONDITIONS
Operating voltage range (Notes 2 and 3)
Timekeeping operating range
(Notes 2 and 4)
(Note 3)
EOSC
= 0
(Notes 4 and 5)
EOSC
= 1 (Note 4)
(Note 2)
(Note 2)
SDA, SQW/INT high impedance
V
OL
= 0.4V (V
CC
> 2.4V), SDA, SQW/INT
V
OL
= 0.2V
CC
(1.3V < V
CC
< 2.4V), SQW/INT
0.7 x
V
CC
-0.3
-1
SQW = 32kHz
SQW = 0
MIN
2.4
1.3
35
600
400
25
TYP
MAX
5.5
5.5
90
1300
800
100
V
CC
+
0.3
0.3 x
V
CC
+1
3
0.250
V
μA
nA
nA
V
V
μA
mA
UNITS
ELECTRICAL CHARACTERISTICS
(V
CC
= 2.4V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SCL Clock Frequency (Note 6)
Bus-Free Time Between a STOP
and START Condition
Hold Time (Repeated) START
Condition (Note 7)
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for Repeated START
Condition
Data Hold Time (Notes 8 and 9)
SYMBOL
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
CONDITIONS
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
MIN
100
0.04
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0
0
TYP
MAX
400
100.00
UNITS
kHz
μs
μs
μs
μs
μs
0.9
μs
2
_______________________________________________________________________________________
I
2
C, 32-Bit, Binary Counter Clock with 64-Bit ID
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.4V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
Data Setup Time (Note 10)
SYMBOL
t
SU:DAT
CONDITIONS
Fast mode
Standard mode
Fast mode
t
R
Standard mode
Fast mode
t
F
Standard mode
t
SU:STO
C
B
C
I/O
TSP
t
OSF
T
_TIMEOUT
25
10
30
100
35
Fast mode
Standard mode
MIN
100
250
20 +
0.1C
B
20 +
0.1C
B
20 +
0.1C
B
20 +
0.1C
B
0.6
4.0
400
300
ns
1000
300
ns
300
μs
pF
pF
ns
ms
ms
TYP
MAX
UNITS
ns
DS1372
Rise Time of SDA and SCL
Signals (Note 11)
Fall Time of SDA and SCL Signals
(Note 11)
Setup Time for STOP Condition
Capacitive Load for Each Bus
Line (Note 11)
I/O Capacitance
SCL Spike Suppresion
Oscillator Stop Flag (OSF) Delay
(Note 12)
Timeout Interval (Note 13)
CRYSTAL SPECIFICATIONS
PARAMETER
Nominal Frequency
Capacitive Load
Equivalent Series Resistance
SYMBOL
f
O
C
L
ESR
MIN
TYP
32.768
12.5
50
MAX
UNITS
kHz
pF
k
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Limits at -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
SCL clocking at maximum frequency = 400kHz.
Specified with I
2
C bus inactive, SCL = SDA = V
CC
.
Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
The I
2
C minimum operating frequency is imposed by the requirement of timeout period.
The first clock pulse is generated after this period.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
IHMIN
of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
must only be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
≥
250ns must then be met.
This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch
the low period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+ t
SU:DAT
= 1000 + 250 = 1250ns
before the SCL line is released.
C
B
= Total capacitance of one bus line in pF.
The parameter t
OSF
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
2.4V
≤
V
CC
≤
V
CC(MAX)
.
The DS1372 can detect any single SCL clock held low longer than T
_TIMEOUT
(MIN). The I
2
C interface is in reset state and
can receive a new START condition when SCL is held low for at least T
_TIMEOUT
(MAX). Once the part detects this condi-
tion the SDA output is released. The oscillator must be running for this function to work.
_______________________________________________________________________________________
3
I
2
C, 32-Bit, Binary Counter Clock with 64-Bit ID
DS1372
Pin Description
PIN
NAME
FUNCTION
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for
operation with a crystal having a 12.5pF specified load capacitance (C
L
). Pin X1 is the input to the
oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the
internal oscillator, pin X2, is floated if an external oscillator is connected to pin X1.
Slave Address Input. This pin is the slave address input for the I
2
C serial interface and is used to
access multiple devices on the same bus. To select the device, the address value on the pin
must match the corresponding bit in the device addresses. This pin can be connected to V
CC
or
ground or be driven to a logic-high or logic-low level.
Ground
Serial Data Input/Output. This pin is the data input/output for the I
2
C serial interface. The SDA pin is
open drain and requires an external pullup resistor.
Serial Clock Input. This pin is the clock input for the I
2
C serial interface and is used to synchronize
data movement on the serial interface.
Square Wave or Active-Low Interrupt Open-Drain Output. This pin is used to output the square wave
or alarm interrupt signal. The function of this pin is selected by the state of the INTCN control bit.
This pin is open drain and requires an external pullup resistor.
DC Power Pin. This pin should be decoupled using a 0.1μF or 1.0μF capacitor.
1, 2
X1, X2
3
AD0
4
5
6
GND
SDA
SCL
7
8
SQW/INT
V
CC
RS[2:1]
DIVIDER CHAIN
X1
÷4
X2
OSCILLATOR
V
CC
GND
SDA
SCL
AD0
I
2
C
INTERFACE
64-BIT ID
ROM
1Hz
÷4096
CLR
32-BIT
COUNTER
24-BIT ALARM
COUNTER
ACE
AF
INTCN
CONTROL/
STATUS
÷2
÷4096
32,768Hz
8192Hz
4096Hz
1Hz
MUX
SQW
MUX
N
SQW/INT
POWER
DS1372
Figure 1. Block Diagram
4
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I
2
C, 32-Bit, Binary Counter Clock with 64-Bit ID
Detailed Description
The DS1372 is a 32-bit binary counter designed to con-
tinuously count time in seconds. An additional counter
is provided that can generate a periodic alarm. An
interrupt output can be driven when the alarm condition
is met. The device includes a unique, factory-lasered
64-bit ROM ID. The device is programmed serially by
an I
2
C bidirectional bus.
DS1372
CRYSTAL
X1
X2
Oscillator Circuit
The DS1372 is designed to operate with a standard
32.768kHz quartz crystal having a 12.5pF specified
load capacitance (C
L
). For more information on crystal
selection and crystal layout considerations, refer to
Application Note 58:
Crystal Considerations with Dallas
Real-Time Clocks (RTCs).
An external 32.768kHz oscil-
lator can be used as the DS1372’s time base. In this
configuration, the X1 pin is connected to the external
oscillator signal and the X2 is floated. The
EOSC
bit in
the Control Register controls oscillator operation.
LOCAL GROUND PLANE (LAYER 2)
Figure 2. Layout Example
Operation
The block diagram in Figure 1 shows the DS1372’s main
elements. As shown, communications to and from the
DS1372 occur serially over an I
2
C bidirectional bus. The
DS1372 operates as a slave device on the serial bus.
Access is obtained by implementing a START condition
and providing a device identification code followed by a
register address. Subsequent registers can be accessed
sequentially until a STOP condition is executed.
Clock Accuracy
The initial clock accuracy is dependent upon the accu-
racy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and
the capacitive load for which the crystal was trimmed.
Additional error is added by crystal frequency drift
caused by temperature shifts. External circuit noise cou-
pled into the oscillator circuit can result in the clock run-
ning fast. Figure 2 shows a typical PCB layout for
isolation of the crystal and oscillator from noise. Refer to
Application Note 58:
Crystal Considerations with Dallas
Real-Time Clocks (RTCs)
for detailed information.
Address Map
Table 1 shows the address map for the DS1372 regis-
ters. During a multibyte access, when the address
pointer reaches the end of the register space (10h) it
wraps around to location 00h. On an I
2
C START or
address pointer incrementing to location 00h, the cur-
rent time is transferred to a second set of registers. The
time information is read from these secondary registers,
while the clock may continue to run. This eliminates the
need to reread the registers in case the main registers
update during a read.
Clock Operation
The clock counter is a 32-bit up counter. The counter
counts up once per second. The contents can be read
or written by accessing the address range 00h–03h. On
an I
2
C START, or when the address pointer rolls over to
00h, the current value is latched into a register, which is
output on the serial data line while the counter contin-
ues to increment. When writing to the registers, the
divider chain is reset when register 00h is written. Once
the divider chain is reset, the remaining clock registers
should be written within one second to avoid rollover
issues. Additionally, to avoid rollover issues the clock
registers must also be written from LSB to MSB, and all
four bytes should always be written.
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