Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers
DESCRIPTION
The DG428, DG429 analog multiplexers have on-chip
address and control latches to simplify design in
microprocessor based applications. Break-before-make
switching action protects against momentary crosstalk of
adjacent input signals.
The DG428 selects one of eight single-ended inputs to a
common output, while the DG429 selects one of four
differential inputs to a common differential output.
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages up to
the power supply rails. An enable (EN) function allows the
user to reset the multiplexer/demultiplexer to all switches off
for stacking several devices. All control inputs, address (A
x
)
and enable (EN) are TTL compatible over the full specified
operating temperature range.
The silicon-gate CMOS process enables operation over a
wide range of supply voltages. The absolute maximum
voltage rating is extended to 44 V. Additionally, single supply
operation is also allowed and an epitaxial layer prevents
latchup.
On-board TTL-compatible address latches simplify the digital
interface design and reduce board space in bus-controlled
systems such as data acquisition systems, process controls,
avionics, and ATE.
FEATURES
•
Halogen-free according to IEC 61249-2-21
Definition
• Low R
DS(on)
: 55
• Low Charge Injection: 1 pC
• On-Board TTL Compatible Address Latches
• High Speed - t
TRANS
: 160 ns
• Break-Before-Make
• Low Power Consumption: 0.3 mW
• Compliant to RoHS Directive 2002/95/EC
BENEFITS
• Improved System Accuracy
•
Microprocessor Bus Compatible
•
Easily Interfaced
•
Reduced Crosstalk
•
High Throughput
•
Improved Reliability
APPLICATIONS
• Data Acquisition Systems
•
Automatic Test Equipment
•
Avionics and Military Systems
•
Communication Systems
•
Microprocessor-Controlled Analog Systems
•
Medical Instrumentation
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG428
Dual-In-Line
A0
WR
A
0
EN
V-
S
1
S
2
S
3
S
4
D
1
2
3
4
5
6
7
8
9
Latches
Decoders/Drivers
18
17
16
15
14
13
12
11
10
RS
A
1
A
2
GND
V+
S
5
S
6
S
7
S
8
9
S4
EN
V-
S
1
S
2
S
3
4
5
6
7
8
DG428
PLCC
WR
A1
NC
1
RS
3
2
20 19
Latches
Decoders/Drivers
18
17
16
15
14
A
2
GND
V+
S
5
S
6
10 11 12 13
S8
NC
S7
D
Top View
Top View
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
www.vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
DG428, DG429
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG429
Dual-In-Line and SOIC
A0
WR
A
0
EN
V-
S
1a
S
2a
S
3a
S
4a
D
a
1
2
3
4
5
6
7
8
9
Latches
Decoders/Drivers
18
17
16
15
14
13
12
11
10
RS
A
1
GND
V+
S
1b
S
2b
S
3b
S
4b
D
b
9
S4a
10 11 12 13
S4b
Da
NC
Db
EN
V-
S
1a
S
2a
S
3a
4
5
6
7
8
Latches
Decoders/Drivers
18
17
16
15
14
GND
V
DD
S
1b
S
2b
S
3b
DG429
PLCC
WR
A1
NC
1
RS
3
2
20 19
Top View
Top View
TRUTH TABLE - DG428
8-Channel Single-Ended Multiplexer
A
2
A
1
A
0
EN
WR
RS
On Switch
Maintains previous
switch condition
None (latches
cleared)
None
1
2
3
4
5
6
7
8
TRUTH TABLE - DG429
Differential 4-Channel Multiplexer
A
1
Latching
A
0
EN
WR
RS
On Switch
Maintains previous
switch condition
None (latches
cleared)
None
1
2
3
4
Latching
X
Reset
X
X
X
X
X
0
X
X
X
1
X
Reset
X
X
X
1
X
X
X
0
Transparent Operation
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Transparent Operation
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
Logic "0" = V
AL
0.8
V
Logic "1" = V
AH
2.4
V
X = Don’t Care
ORDERING INFORMATION - DG428
Temp Range
Package
18-pin Plastic DIP
- 40 °C to 85 °C
20-pin PLCC
Part Number
DG428DJ
DG428DJ-E3
DG428DN
DG428DN-E3
ORDERING INFORMATION - DG429
Temp Range
Package
18-pin Plastic DIP
- 40 °C to 85 °C
20-pin PLCC
18-pin Widebody SOIC
Part Number
DG429DJ
DG429DJ-E3
DG429DN
DG429DN-E3
DG429DW
DG429DW-E3
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Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
DG428, DG429
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
Voltages Referenced to V-
Digital Inputs
a
,
Parameter
V+
GND
Symbol
Limit
44
25
(V-) - 2 V to (V+) + 2 V
or 30 mA, whichever occurs first
30
100
- 65 to 150
- 65 to 125
470
900
800
450
Unit
V
V
S
, V
D
Current (Any Terminal)
Peak Current, S or D (Pulsed at 1 ms, 10 % Duty Cycle Max)
Storage Temperature
(AK Suffix)
(DJ, DN Suffix)
18-pin Plastic DIP
c
Power Dissipation (Package)
b
18-pin CerDIP
d
20-pin PLCC
f
mA
°C
mW
28-Pin Widebody SOIC
f
Notes:
a. Signals on S
X
, D
X
or IN
X
exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6.3 mW/°C above 75 °C.
d. Derate 12 mW/°C above 75 °C.
e. Derate 10 mW/°C above 75 °C.
f. Derate 6 mW/°C above 75 °C.
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
www.vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
DG428, DG429
Vishay Siliconix
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V, WR = 0,
RS = 2.4 V, V
IN
= 2.4 V, 0.8 V
f
Temp.
b
Full
V
D
= ± 10 V, V
AL
= 0.8 V
I
S
= - 1 mA, V
AH
= 2.4 V
- 10 V < V
S
< 10 V
I
S
= - 1 mA
V
S
= ± 10 V,
V
EN
= 0 V, V
D
= ± 10 V
V
EN
= 0 V
V
D
= ± 10 V
V
S
= ± 10 V
V
S
= V
D
= ± 10 V
V
EN
= 2.4 V
V
AL
= 0.8 V
V
AH
= 2.4 V
V
A
= 2.4 V
V
A
= 15 V
V
EN
= 0 V, 2.4 V, V
A
= 0 V
RS = 0 V, WR = 0 V
f = 1 MHz
DG428
DG429
DG428
DG429
Room
Full
Room
Room
Full
Room
Full
Room
Full
Room
Full
Room
Full
Full
Full
Full
Room
Room
Full
Full
Room
Full
Room
Full
Room
55
A Suffix
- 55 °C to 125 °C
Typ.
c
Min.
d
- 15
Max.
d
15
100
125
D Suffix
- 40 °C to 85 °C
Min.
d
- 15
Max.
d
15
100
125
Unit
V
%
- 0.5
- 50
-1
- 100
-1
- 50
-1
- 100
-1
- 50
0.5
50
1
100
1
50
1
100
1
50
1
1
-1
-1
pF
250
300
10
150
225
150
300
10
150
225
150
300
ns
250
300
- 0.5
- 50
-1
- 100
-1
- 50
-1
- 100
-1
- 50
0.5
50
1
100
1
50
1
100
1
50
1
1
µA
Parameter
Analog Switch
Analog Signal Range
e
Drain-Source
On-Resistance
Greatest Change in R
DS(on)
Between Channels
g
Symbol
V
ANALOG
R
DS(on)
R
DS(on)
I
S(off)
5
± 0.03
± 0.07
± 0.05
± 0.07
± 0.05
Source Off Leakage Current
Drain Off Leakage Current
I
D(off)
nA
Drain On Leakage Current
I
D(on)
Digital Control
Logic Input Current
Input Voltage High
Logic Input Current
Input Voltage Low
Logic Input Capacitance
Dynamic Characteristics
Transition Time
Break-Before-Make Interval
Enable and Write Turn-On Time
Enable and Reset Turn-Off Time
Charge Injection
t
TRANS
t
OPEN
t
ON(EN,WR)
t
OFF(EN,RS)
Q
See Figure 5
See Figure 4
See Figure 6 and 7
See Figure 6 and 8
V
GEN
= 0 V, R
GEN
= 0
C
L
= 1 nF, See Figure 9
V
EN
= 0 V, R
L
= 300
C
L
= 15 pF, V
S
= 7 V
RMS
f = 100 kHz
V
S
= 0 V, V
EN
= 0 V, f = 1 MHz
V
D
= 0 V
V
EN
= 0 V
f = 1 MHz
DG428
DG429
DG428
DG429
150
30
90
55
1
I
AH
I
AL
C
in
0.01
0.01
- 0.01
8
pC
Off Isolation
Source Off Capacitance
Drain Off Capacitance
Drain On Capacitance
OIRR
C
S(off)
C
D(off)
C
D(on)
Room
Room
Room
Room
Room
Room
Full
- 75
11
40
20
54
34
100
100
10
100
20
- 0.001
-5
100
-5
100
100
10
100
100
dB
pF
Minimum Input Timing Requirements
t
W
Write Pulse Width
A
X
, EN Data Set Up time
A
X
, EN Data Hold Time
Reset Pulse Width
Power Supplies
Positive Supply Current
Negative Supply Current
I+
I-
V
EN
= V
A
= 0, RS = 5 V
t
S
t
H
t
RS
V
S
= 5 V, See Figure 3
See Figure 2
Full
Full
Full
Room
Room
ns
µA
www.vishay.com
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Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
DG428, DG429
Vishay Siliconix
SPECIFICATIONS
a
(for single supply)
Test Conditions
Unless Otherwise Specified
V+ = 12 V, V- = 0 V, WR = 0,
RS = 2.4 V, V
IN
= 2.4 V, 0.8 V
f
A Suffix
- 55°C to 125 °C
Temp.
b
Typ.
c
Full
V
D
= ± 10 V, V
AL
= 0.8 V
I
S
= - 500 µA, V
AH
= 2.4 V
0 V < V
S
< 10 V
I
S
= - 1 mA
V
S
= 0 V, 10 V,
V
EN
= 0 V, V
D
= 10 V, 0 V
V
D
= 0 V, 10 V
V
S
= 10 V, 0 V
V
EN
= 0 V
V
S
= V
D
= 0 V, 10 V
V
EN
= 2.4 V
V
AL
= 0.8 V
V
AH
= 2.4 V
DG428
DG429
DG428
DG429
Room
Room
Room
Full
Room
Full
Room
Full
Room
Full
Room
Full
Full
Full
Full
-1
80
5
± 0.03
± 0.07
± 0.05
± 0.07
± 0.05
- 0.5
- 50
-1
- 100
-1
- 50
-1
- 100
-1
- 50
0.5
50
1
100
1
50
1
100
1
50
1
1
-1
- 0.5
- 50
-1
- 100
-1
- 50
-1
- 100
-1
- 50
0.5
50
1
100
1
50
1
100
1
50
1
1
Min.
d
0
Max.
d
12
150
D Suffix
- 40 °C to 85 °C
Min.
d
0
Max.
d
12
150
Unit
V
%
Parameter
Analog Switch
Analog Signal Range
e
Drain-Source
On-Resistance
R
DS(on)
Match
g
Source Off Leakage Current
Symbol
V
ANALOG
R
DS(on)
R
DS(on)
I
S(off)
Drain Off Leakage Current
I
D(off)
nA
Drain On Leakage Current
Digital Control
Logic Input Current
Input Voltage High
Logic Input Current
Input Voltage Low
Dynamic Characteristics
Transition Time
Break-Before-Make Interval
Enable and WriteTurn-On Time
Enable and Reset Turn-Off Time
Charge Injection
Off Isolation
I
D(on)
I
AH
I
AL
V
A
= 2.4 V
V
A
= 12 V
V
EN
= 0 V, 2.4 V, V
A
= 0 V
RS = 0 V, WR = 0 V
S
1
= 10 V/ 2 V, S
8
= 2 V/ 10 V
See Figure 5
See Figure 4
S
1
= 5 V
See Figure 6 and 7
S
1
= 5 V
See Figure 6 and 8
V
GEN
= 6 V, R
GEN
= 0
C
L
= 1 nF, See Figure 9
V
EN
= 0 V, R
L
= 300
C
L
= 15 pF, V
S
= 7 V
RMS
f = 100 kHz
µA
t
TRANS
t
OPEN
t
ON(EN,WR)
t
OFF(EN,RS)
Q
OIRR
Room
Full
Room
Full
Room
Full
Room
Full
Room
Room
160
40
110
70
4
- 75
25
10
280
350
25
10
300
400
300
400
280
350
ns
300
400
300
400
pC
dB
Minimum Input Timing Requirements
t
W
Write Pulse Width
A
X
, EN Data Set Up time
t
S
t
H
A
X
, EN Data Hold Time
t
RS
Reset Pulse Width
Power Supplies
Positive Supply Current
I+
See Figure 2
V
S
= 5 V, See Figure 3
V
EN
= 0 V, V
A
= 0, RS = 5 V
Full
Full
Full
Full
Room
20
100
100
10
100
100
100
100
10
100
100
ns
µA
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. V
IN
= input voltage to perform proper function.
g.
R
DS(on)
= R
DS(on)
MAX – R
DS(on)
MIN
R
DS(on)
AVE
(
)
x 100 %
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
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