AT97SC3205
Trusted Platform Module – SPI Interface
SUMMARY DATASHEET
Features
Compliant to the Trusted Computing Group (TCG) Trusted Platform Module
(TPM) Version 1.2 Specification
Compliant with TCG PC Client-Specific TPM Interface Specification (TIS)
Version 1.3
Single-chip, Turnkey Solution
Hardware Asymmetric Crypto Engine
Atmel
®
AVR
®
RISC Microprocessor
Internal EEPROM Storage for RSA Keys
Serial Peripheral Interface (SPI) Protocol Up to 45MHz*
(*Typical PC Operating Range is 24MHz to 33MHz)
Secure Hardware and Firmware Design and Chip Layout
FIPS-140-2 Module Certified Including the High-quality Random Number
Generator (RNG), HMAC, AES, SHA, and RSA Engines
NV Storage Space for 2066 bytes of User Defined Data
3.3V Supply Voltage
28-lead Thin TSSOP and 32-pad QFN Package
Offered in Both Commercial (0°C to 70°C) and Industrial (-40°C to +85°C)
Temperature Ranges
Description
The Atmel AT97SC3205 is a fully integrated security module designed to be
integrated into personal computers and other embedded systems. It implements
version 1.2 of the Trusted Computing Group (TCG) specification for Trusted
Platform Modules (TPM).
This is a summary document.
The complete document is
available under NDA. For more
information, please contact
your local Atmel sales office.
Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014
1.
Pin Configurations and Pinouts
Table 1-1.
Pin Name
V
CC
GND
GPIO Express-00
PP/GPIO
GPIO
MISO
MOSI
PIRQ#
SPI_CLK
SPI_CS#
SPI_RST#
TestI
TestBI
XTamper
NC
Pin Configurations
Function
3.3V Supply Voltage
Ground
GPIO assigned to TPM_NV_INDEX_GPIO_00
Hardware Physical Presence or GPIO pin.
General Purpose Input/Output Pin
SPI Slave Data Output
SPI Slave Data Input
SPI Interrupt Requests
SPI Clock Input
SPI Chip Select
SPI Reset Pin
TestI Manufacturing Test Input (Disabled)
TestBI Manufacturing Test Input (Disabled)
Indicate External Tamper Event
No Connect
Figure 1-1. Pinouts
28-pin TSSOP
4.40mm x 9.70mm Body
0.65mm Pitch
32-pin QFN
4.00mm x 4.00mm Body
0.90mm Pitch
GPIO2
GPIO1
GND
NC
NC
NC
NC
NC
GPIO1
V
CC
GND
NC
GPIO Express-00
PP/GPIO
TestI
TestBI/GPIO/XTamper
2
3
4
5
6
7
8
9
27 NC
26 MISO
25 GND
24 V
CC
23 MOSI
22 SPI_CS#
21 SPI_CLK
20 PIRQ#
19 V
CC
18 GND
17 GPIO3
16 SPI_RST#
15 NC
V
CC
GND
GPIO Express-00
PP/GPIO
TestI
TestBI/GPIO/XTamper
NC
V
CC
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24 MISO
23 GND
22 V
CC
21 MOSI
20 SPI_CS#
19 SPI_CLK
18 PIRQ#
17 SPI_RST#
9 10 11 12 13 14 15 16
GND
NC
NC
NC
NC
GPIO3
NC
V
CC
10
GND 11
NC 12
NC 13
NC 14
2
AT97SC3205 [SUMMARY DATASHEET]
Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014
NC
GPIO2
1
28 NC
2.
Block Diagram
ROM
Program
EEPROM
Program
AVR
8-bit RISC
CPU
GPIO Express-00
PP/GPIO
SRAM
GPIO
EEPROM
Data
MOSI
MISO
SPI_CLK
SPI_CS#
PIRQ#
SPI_RST#
Timer
Physical
Security
Circuitry
SPI
RNG
CRYPTO
Engine
The TPM includes hardware Random Number Generator (RNG), including a FIPS certified Pseudo Random
Number Generator that is used for key generation and TCG protocol functions. The RNG is also available to the
system to generate random numbers that may be needed during normal operation.
The chip uses a dynamic internal memory management scheme to store multiple RSA keys. Other than the
standard TCG commands (TPM_FlushSpecific, TPM_Loadkey2), no system intervention is required to manage
this internal key cache.
The TPM is offered to OEM and ODM manufacturers as a turnkey solution, including the firmware integrated on the
chip. In addition, Atmel provides the necessary device driver software for integration into certain operating
systems, along with BIOS drivers. Atmel will also provide manufacturing support software for use by OEMs and
ODMs during initialization and verification of the TPM during board assembly.
Full documentation for TCG primitives can be found in the TCG TPM Main Specification, Parts 1 to 3, on the TCG
web site located at
https://www.trustedcomputinggroup.org.
TPM features specific to PC client platforms are
specified in the TCG PC Client Specific TPM Interface Specification, version 1.3, also available on the TCG web
site. Implementation guidance for PC platforms is outlined in the TCG PC Client Specific Implementation
Specification for Conventional Bios, version 1.2, also available on the TCG web site.
AT97SC3205 [SUMMARY DATASHEET]
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3
3.
Pin Description
=
Table 3-1.
Pin
Pin Descriptions
Description
Power Supply, 3.3V.
Care should be taken to prevent excessive noise. Effective decoupling of the V
CC
inputs to the
Atmel TPM is critical to assure consistently reliable operation over the lifetime of the system. The Atmel
recommendation is for a decoupling bypass capacitor within the range of 2200pF to 4700pF, to be placed as close as
possible, < 5mm, to each of the V
CC
pins, located between each V
CC
pin and the immediately adjacent GND pin. A
0.1μF decoupling bypass capacitor should be placed at the node in which these V
CC
traces join, which should be as
close as possible, < 10mm, to the TPM. In all cases, this bypass capacitor should be closer than the next closest
component. All capacitors should be of high quality, with dielectric ratings of X5R or X7R. A low-power state is
automatically entered when the chip is idle. No further action is required by the system to enter low-power mode.
System Ground.
General Purpose Input/Output. Internal pull-up resistor.
This pin is mapped to NV Index
TPM_NV_INDEX_GPIO_00. Default TPM configuration: GPIO Input. GPIO-Express-00 also serves as the XOR
chain Output during I/O test mode. Since GPIO-Express-00 has an internal pull-up, it should be left floating if unused.
General Purpose Input/Output. Internal pull-down resistor.
This pin is an indicator for hardware physical
presence; active high. Default TPM configuration: GPIO input. Since PP/GPIO has an internal pull-down, it should be
left floating if unused.
General Purpose Input/Output.
If unused, this pin can be tied to GND or V
CC
at the customers discretion.
Master In Slave Out. SPI Slave Data Output.
This pin serves as the SPI Data output from the TPM.
Master Out Slave In. SPI Slave Data Input.
This pin serves as the SPI Data Input to the TPM.
SPI Interrupt Pin, Active-low.
This pin is used by the TPM to assert interrupts. If unused, this pin should be tied to
ground directly or through a 4.7K resistor.
Clock used to drive the SPI bus.
This pin should be asserted high for power savings when the TPM is not in use.
SPI_CS# Chip Select, Active-low.
The TPM chip select.
SPI Reset Pin, Active-low.
Pulsing this signal low resets the internal state of the TPM, and is equivalent to
removal/restoration of power to the chip. The required minimum reset pulse width is 2μs. On power-up, it is critical
that reset be kept active-low until V
CC
, and SPI_CLK stabilize. To be compliant with TCG requirements, this pin
needs to be tied to system reset. TPM_Init is indicated by asserting this pin.
TestI Manufacturing Test Input.
Disabled after manufacturing. Tie TestI to ground directly or through a 4.7k
resistor.
TestBI Manufacturing Test Input.
The Atmel TPM does not support legacy addressing via the optional BADD
implementation of this pin.The TestBI pin also serves as the XTamper pin or an additional GPIO pin, active high.
(See the application note, “Atmel Specific TPM Commands Reference Guide” for details on XTamper
implementation). If unused, this pin should be tied to ground directly or through a 4.7K resistor.
No Connect Pins (TSSOP).
The AT97SC3205 TSSOP package has additional pins which are no connects and can be tied to GND, V
CC
, or left
floating at the customers discretion:
NC – TSSOP Pin 5
NC – TSSOP Pin 12
NC – TSSOP Pin 13
NC – TSSOP Pin 14
NC – TSSOP Pin 15
NC – TSSOP Pin 27
NC – TSSOP Pin 28
V
CC
GND
GPIO Express-00
PP/GPIO
GPIO
MISO
MOSI
PIRQ#
SPI_CLK
SPI_CS#
SPI_RST#
TestI
TestBI/GPIO/
XTamper
NC
4
AT97SC3205 [SUMMARY DATASHEET]
Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014
Table 3-1.
Pin
Pin Descriptions (Continued)
Description
No Connect Pins (QFN).
The AT97SC3205 QFN package has additional pins which are no connects and can be tied to GND, V
CC
, or left
floating at the customers discretion:
NC – QFN Pin 7
NC – QFN Pin 10
NC – QFN Pin 11
NC – QFN Pin 13
NC
NC – QFN Pin 14
NC – QFN Pin 15
NC – QFN Pin 16
NC – QFN Pin 25
NC – QFN Pin 26
NC – QFN Pin 27
NC – QFN Pin 28
NC – QFN Pin 31
Note:
1.
The substrate center pad for the 32-pin QFN is directly tied to GND internally; therefore, this pad can either be left
floating or tied to GND.
AT97SC3205 [SUMMARY DATASHEET]
Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014
5
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