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SY10EP53VKG

Description
Flip Flops 3.3V/5V Differential Data and Clock D Flip Flop with Set & Reset
Categorylogic    logic   
File Size57KB,7 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
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SY10EP53VKG Overview

Flip Flops 3.3V/5V Differential Data and Clock D Flip Flop with Set & Reset

SY10EP53VKG Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrochip
package instructionMSOP-10
Reach Compliance Codecompliant
Other featuresNECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
series10E
JESD-30 codeS-PDSO-G10
JESD-609 codee4
length3 mm
Logic integrated circuit typeD FLIP-FLOP
Humidity sensitivity level2
Number of digits1
Number of functions1
Number of terminals10
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeSQUARE
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)0.35 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyECL
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
Trigger typePOSITIVE EDGE
width3 mm
Micrel, Inc.
5V/3.3V DIFFERENTIAL DATA
AND CLOCK D FLIP-FLOP WITH
SET AND RESET
ECL Pro™
SY10EP53V
ECL Pro™
SY10EP53V
FEATURES
3.3V and 5V power supply options
3.0GHz toggle frequency
75K
internal input pulldown resistors
Available in 10-pin MSOP package
ECL Pro™
DESCRIPTION
The SY10EP53V is a differential data, differential clock
D flip-flop with set and reset. The EP53V is ideally suited
for those applications which require the ultimate in AC
performance.
Data enters the master portion of the flip-flop when
the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock.
The differential clock inputs also allow the EP53V to be
used as a negative edge triggered device. Both set and
reset inputs are asynchronous, level triggered signals.
The EP53V employs input clamping circuitry so that,
under open input conditions (pulled down to V
EE
), the
outputs of the device will remain stable.
PIN NAMES
Pin
D, /D
CLK, /CLK
Q, /Q
V
CC
, V
EE
SET
RESET
Function
Data Input (ECL)
Clock Input (ECL)
Data Output (ECL)
Power Supply
ECL Asynchonous Set
ECL Asynchonous Reset
TRUTH TABLE
(1)
D
L
H
X
X
X
Note 1.
SET
L
L
H
L
H
RESET
L
L
L
H
H
CLK
Z
Z
X
X
X
Q
L
H
H
L
UNDEF
Z = LOW-to-HIGH transition.
ECL Pro is a trademark of Micrel, Inc.
M9999-011508
hbwhelp@micrel.com or (408) 955-1690
Rev.: E
Amendment: /0
1
Issue Date: January 2008

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