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IS61LV12816L-10BLI-TR

Description
SRAM 2Mb 128Kx16 10ns Async SRAM 3.3v
Categorystorage   
File Size110KB,17 Pages
ManufacturerISSI(Integrated Silicon Solution Inc.)
Websitehttp://www.issi.com/
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IS61LV12816L-10BLI-TR Overview

SRAM 2Mb 128Kx16 10ns Async SRAM 3.3v

IS61LV12816L-10BLI-TR Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerISSI(Integrated Silicon Solution Inc.)
Product CategorySRAM
RoHSDetails
Memory Size2 Mbit
Organization128 k x 16
Access Time10 ns
Interface TypeParallel
Supply Voltage - Max3.6 V
Supply Voltage - Min3.135 V
Supply Current - Max65 mA
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT
Package / CaseTFBGA-48
PackagingReel
Data RateSDR
TypeAsynchronous
Number of Ports1
Moisture SensitiveYes
NumOfPackaging1
Factory Pack Quantity2500
IS61LV12816L
128K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
FEATURES
High-speed access time: 8, 10 ns
Operating Current: 50mA (typ.)
Stand by Current: 700µA (typ.)
TTL and CMOS compatible interface levels
Single 3.3V power supply
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Lead-free available
ISSI
OCTOBER 2005
®
DESCRIPTION
The
ISSI
IS61LV12816L is a high-speed, 2,097,152-bit
static RAM organized as 131,072 words by 16 bits. It is
fabricated using
ISSI
's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times
as fast as 8 ns with low power consumption.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE.
The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61LV12816L is packaged in the JEDEC standard
44-pin TSOP (Type II), 44-pin LQFP, and 48-pin mini BGA
(6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128Kx16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
10/27/05
1

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Description SRAM 2Mb 128Kx16 10ns Async SRAM 3.3v Array/Network Resistor, Isolated, Tantalum Nitride/nickel Chrome, 0.1W, 6900ohm, 100V, 0.5% +/-Tol, -100,100ppm/Cel, 2617, SRAM 2Mb 128Kx16 10ns Async SRAM 3.3v Fixed Resistor, Wire Wound, 0.5W, 97.6ohm, 400V, 0.25% +/-Tol, -20,20ppm/Cel, SRAM 2Mb 128Kx16 10ns Async SRAM 3.3v SRAM 2Mb 128Kx16 10ns Async SRAM 3.3v SRAM 2Mb 128Kx16 10ns Async SRAM 3.3v
Is it Rohs certified? - incompatible - conform to conform to conform to -
Reach Compliance Code - compliant - compliant compliant compliant -
ECCN code - EAR99 - EAR99 3A991.B.2.A 3A991.B.2.A -
Number of terminals - 20 - 2 48 44 -
Minimum operating temperature - -55 °C - -55 °C -40 °C -40 °C -
Package form - SMT - Axial GRID ARRAY, THIN PROFILE, FINE PITCH FLATPACK, LOW PROFILE -
technology - TANTALUM NITRIDE/NICKEL CHROME - WIRE WOUND CMOS CMOS -
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