74AC273MTCX datasheet, PDF - EEWORLD Datasheet

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74AC273MTCX: DescriptionFlip Flops Oct D-Type Flip-Flop; Categorylogic logic; File Size371KB，12 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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74AC273MTCX Overview

Flip Flops Oct D-Type Flip-Flop

74AC273MTCX Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Fairchild
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP20,.25
Contacts	20
Reach Compliance Code	unknown
series	AC
JESD-30 code	R-PDSO-G20
JESD-609 code	e3
length	6.5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Sup	75000000 Hz
MaximumI(ol)	0.012 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP20,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3/5 V
propagation delay (tpd)	14.5 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	4.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	4.4 mm
minfmax	125 MHz
Base Number Matches	1

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74AC273, 74ACT273 — Octal D-Type Flip-Flop

January 2008

74AC273, 74ACT273

Octal D-Type Flip-Flop

Features

■

Ideal buffer for microprocessor or memory

■

Eight edge-triggered D-type flip-flops

■

Buffered common clock

■

Buffered, asynchronous master reset

■

See 377 for clock enable version

■

See 373 for transparent latch version

■

See 374 for 3-STATE version

■

Outputs source/sink 24mA

■

74ACT273 has TTL-compatible inputs

General Description

The AC273 and ACT273 have eight edge-triggered

D-type flip-flops with individual D-type inputs and Q

outputs. The common buffered Clock (CP) and Master

Reset (MR) input load and reset (clear) all flip-flops

simultaneously.

The register is fully edge-triggered. The state of each

D-type input, one setup time before the LOW-to-HIGH

clock transition, is transferred to the corresponding flip-

flop's Q output.

All outputs will be forced LOW independently of Clock or

Data inputs by a LOW voltage level on the MR input. The

device is useful for applications where the true output

only is required and the Clock and Master Reset are

common to all storage elements.

Ordering Information

Order Number

74AC273SC

74AC273SJ

74AC273MTC

74AC273PC

74ACT273SC

74ACT273SJ

74ACT273MTC

Package

Number

M20B

M20D

MTC20

N20A

M20B

M20D

MTC20

Package Description

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

74AC273, 74ACT273 Rev. 1.6.0

www.fairchildsemi.com

74AC273MTCX Related Products

	74AC273MTCX	74AC273PC
Description	Flip Flops Oct D-Type Flip-Flop	Flip Flops Oct D-Type Flip-Flop
Is it Rohs certified?	conform to	conform to
Maker	Fairchild	Fairchild
Parts packaging code	TSSOP	DIP
package instruction	TSSOP, TSSOP20,.25	DIP, DIP20,.3
Contacts	20	20
Reach Compliance Code	unknown	unknown
series	AC	AC
JESD-30 code	R-PDSO-G20	R-PDIP-T20
JESD-609 code	e3	e3
length	6.5 mm	26.075 mm
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP
Maximum Frequency@Nom-Sup	75000000 Hz	75000000 Hz
MaximumI(ol)	0.012 A	0.012 A
Number of digits	8	8
Number of functions	1	1
Number of terminals	20	20
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	DIP
Encapsulate equivalent code	TSSOP20,.25	DIP20,.3
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	IN-LINE
Peak Reflow Temperature (Celsius)	260	NOT APPLICABLE
power supply	3.3/5 V	3.3/5 V
propagation delay (tpd)	14.5 ns	14.5 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	5.08 mm
Maximum supply voltage (Vsup)	6 V	6 V
Minimum supply voltage (Vsup)	2 V	2 V
Nominal supply voltage (Vsup)	4.5 V	4.5 V
surface mount	YES	NO
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	THROUGH-HOLE
Terminal pitch	0.65 mm	2.54 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT APPLICABLE
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	4.4 mm	7.62 mm
minfmax	125 MHz	125 MHz

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